A fully functional 32-bit RV32I RISC-V CPU core implemented entirely from scratch in TL-Verilog using the Makerchip online IDE. This project implements a complete single-cycle processor capable of executing real RISC-V instructions across all major instruction categories. The design was verified using an integrated testbench and successfully passes the full instruction test suite.
- Architecture: RV32I, single-cycle CPU
- Design style: Transaction-Level Verilog (TL-Verilog)
- Execution model: Instruction Fetch → Decode → Execute → Memory → Writeback (single-cycle)
- Verification: Makerchip testbench with waveform & visualization analysis
This project demonstrates a full end-to-end CPU microarchitecture, including control flow, arithmetic, branching, memory access, and register management.
The following diagram shows the complete single-cycle RV32I CPU architecture implemented in TL-Verilog. Key components include:
- Program Counter (PC)
- Instruction Memory (IMem)
- Instruction Decode & Control Logic
- Register File (xreg)
- Arithmetic Logic Unit (ALU)
- Data Memory (DMem)
- Write-back and control-flow logic
- Program Counter (PC) with branch & jump control
- Instruction Fetch (IMem)
- Instruction Decode
- Immediate generation (I, S, B, U, J formats)
- 32 × 32-bit Register File (x0–x31)
- Arithmetic Logic Unit (ALU)
- Data Memory (DMem)
- Write-back logic
- ADD, ADDI, SUB, LUI, AUIPC
- AND, ANDI, OR, ORI, XOR, XORI
- SLL, SLLI, SRL, SRLI, SRA, SRAI
- SLT, SLTI, SLTU, SLTIU
- BEQ, BNE, BLT, BGE, BLTU, BGEU
- JAL, JALR
- LW, SW
The CPU was verified using Makerchip’s integrated testbench and simulation environment. Verification included:
- Execution of a full RV32I instruction test program
- Validation of register file contents
- Correct memory read/write behavior
- Branch and jump control-flow correctness
Successful execution is indicated by: Simulation PASSED
Makerchip visualization tools were used to inspect internal CPU state in real time, including:
- Instruction flow
- Control signals
- Register contents
- Memory accesses
- TL-Verilog
- Makerchip IDE
- RISC-V RV32I ISA
- Verilator (via Makerchip)
- Open-source hardware toolchain
✅ Complete single-cycle RV32I CPU
✅ All major instruction categories implemented
✅ Branch, jump, and memory operations verified
✅ Full simulation test suite passed
This project is complete and fully functional.
This project provided hands-on experience with:
- Designing a complete CPU microarchitecture from scratch
- Implementing the RV32I ISA in hardware
- Control-flow logic (branches and jumps)
- Memory interfacing and register file design
- Hardware verification using waveforms and visual debugging tools Building and debugging a full processor core significantly deepened my understanding of how modern CPUs execute instructions at the hardware level.
Bermet Egimbaeva
Inspired by the Building a RISC-V CPU Core course and the open-source hardware ecosystem around RISC-V, Makerchip, and TL-Verilog.