Skip to content

Verilog: KNOWNBUG test for using identifier of instance #1500

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
kroening wants to merge 1 commit into
base: main
Choose a base branch
from
Open

Verilog: KNOWNBUG test for using identifier of instance #1500

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 9 additions & 0 deletions regression/verilog/modules/instance_array2.desc
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
KNOWNBUG
instance_array2.sv

^file .* line 9: no support for instance arrays$
^EXIT=2$
^SIGNAL=0$
--
--
This does not parse.
19 changes: 19 additions & 0 deletions regression/verilog/modules/instance_array2.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,19 @@
// 1800-2017 23.3.3.5

module sub(input i);
endmodule

module main;

sub my_instance[8:1](8'b1111_0000);

initial #1 assert(my_instance[1].i == 0);
initial #1 assert(my_instance[2].i == 0);
initial #1 assert(my_instance[3].i == 0);
initial #1 assert(my_instance[4].i == 0);
initial #1 assert(my_instance[5].i == 1);
initial #1 assert(my_instance[6].i == 1);
initial #1 assert(my_instance[7].i == 1);
initial #1 assert(my_instance[8].i == 1);

endmodule
Loading