FPGA-based parallelism for a 16-QAM wireless communication and Ultrasound POC diagnostic system.
- About the Project
- Getting Started
- Usage
- Results and Demo
- Future Work
- Troubleshooting
- Contributors
- Acknowledgements and Resources
This project demonstrates the potential of Field-Programmable Gate Arrays (FPGAs) by running two very different and complex workloads simultaneously on a single chip: a 16-QAM wireless communication pipeline and a portable Ultrasound Point-of-Care (POC) diagnostic system.
The core innovation is the true parallel execution of a digital communications pipeline and a biomedical imaging pipeline. This leverages the FPGA's unique ability to perform multiple operations at the same time, unlike traditional processors that execute instructions sequentially. This approach results in a highly efficient, reconfigurable, and low-power single-chip solution for real-time signal and image processing.
A Field-Programmable Gate Array (FPGA) is a type of integrated circuit that can be reconfigured or reprogrammed to implement a custom digital circuit. Unlike a microprocessor that executes software instructions sequentially, the hardware logic on an FPGA is hard-wired and executes in parallel. This allows for extremely high performance and low latency, making FPGAs ideal for tasks requiring real-time, high-throughput data processing.
The design process for an FPGA is similar to software programming but with a hardware-centric mindset. In the context of hardware description languages (HDLs) like Verilog:
- Verilog Modules ≈ Functions
- Top Module ≈ Main function
The FPGA's architecture is perfectly suited for a project like EchoCore for three key reasons:
- Single-chip solution: It allows for the integration of both a complex signal processing pipeline for wireless communication and an image processing pipeline for ultrasound onto a single chip, significantly reducing size, power consumption, and cost.
- Re-programmable and power-efficient: Unlike Application-Specific Integrated Circuits (ASICs), FPGAs are flexible and can be reconfigured for different applications or algorithm updates. Their hardware-based parallelism is also far more power-efficient than software-based solutions for similar tasks.
- Enables parallel, real-time performance: The most critical advantage for this project is the FPGA's ability to execute both the 16-QAM and Ultrasound pipelines in parallel, ensuring real-time performance for both data transfer and medical diagnostics.
Quadrature Amplitude Modulation (QAM) is a modulation scheme that encodes data by altering both the amplitude and phase of a carrier signal. 16-QAM is specifically used for this project because it is a high data rate modulation scheme. By representing 4 bits per symbol (2^4 = 16), it efficiently transfers large amounts of data, making it ideal for the wireless image transfer from the ultrasound system to a PC or tablet.
The 16-QAM signal is composed of two carrier waves that are 90 degrees out of phase, known as the in-phase (I) and quadrature (Q) components. The data stream modulates the amplitude of these waves, and the combined signal's unique amplitude and phase create a specific constellation point, which represents the digital symbol.
Signal Flow:
- Data Input: The incoming digital data is grouped into 4-bit chunks.
- Symbol Mapping: The 4-bit chunks are split into two 2-bit components (I and Q), which are then mapped to specific amplitude levels using Gray coding.
- Upsampling: To reduce the signal bandwidth and prevent inter-symbol interference, additional samples are inserted between each symbol.
- Filtering: A Finite Impulse Response (FIR) filter is applied to the upsampled signal to limit its bandwidth and smooth the transitions between symbols.
- Carrier Mixing and Summation: The filtered I and Q components are multiplied onto sine and cosine waves, respectively. These modulated signals are then summed to form the final transmitted QAM signal.
The Ultrasound POC (Point-of-Care) system is a key component of this project, demonstrating how FPGAs can enable portable, real-time medical diagnostics. The system is designed to be a compact and cost-effective ultrasound solution.
The ultrasound signal chain implemented on the FPGA includes:
- Front-End: A 16-channel analog front-end with pulsers, multiplexers, and ADCs to achieve 32-channel performance using an Extended Aperture (EA) technique. This technique improves lateral resolution by using a small number of physical channels.
- Mid-Stage: This stage performs essential signal conditioning, including DC canceling, FIR filters, and time-gain compensation (TGC). A key innovation is the use of a pseudo-dynamic receive beamforming algorithm, which significantly reduces hardware complexity by updating the focusing delay value only at predetermined focal zones, as opposed to every single focusing point.
- Back-End: The final stages perform envelope detection, log compression (using a look-up table), and scan conversion using the CORDIC algorithm to transform the polar coordinate data into Cartesian display data, enabling real-time B-mode imaging.
This FPGA-based design allows the entire ultrasound signal and image processing to be embedded within a single chip, making a powerful, yet portable, diagnostic system a reality.
EchoCore is more than just a tech demo:
- For communications: It shows how efficient modulation (16-QAM) can live on the same chip as other heavy tasks.
- For healthcare: It points toward a future where portable ultrasound devices are accessible and affordable.
- For engineering: It’s proof that parallel workloads (even very different ones) can share a single FPGA.
- FPGA Board: BeagleV Fire
- Toolchain: Libero SoC v2024.2
- HDL: Verilog
- Simulation & Visualization: Python, MATLAB (for GUI & plots),Oscilloscope
EchoCore
├── README.md # Main project documentation
├── assets # Media
│
├── QAM16
│ ├── README.md # QAM implementation details
│ ├── workflow # Block diagrams and workflows
│ ├── media # Screenshots, test results
│ └── libero_files # Libero project files
│
└── Ultrasound
├── README.md # Ultrasound implementation details
├── workflow # Signal chain and beamforming
├── media # Screenshots, test results
├── libero_files # Libero project files
└── scan_coversion # Scan conversion python file
- Verilog coding
- Basic knowledge of Digital Electronics + Signal Processing
- Libero SoC v2024.2
- License setup for Microchip FPGA tools
- ChipVerify
- HDLBits
- Digital Electronics Basics – Playlist 1
- Digital Electronics Basics – Playlist 2
- Signal Processing Basics
- CORDIC Algorithm
- Download Libero v2024.2 (Linux)
- Extract and install
- Setup license
cd ~/Linux_Licensing_Daemon_11.19.6.0_64-bit
./lmgrd -c /path/to/License.dat
./lmutil lmstat -a -c ~/License.dat
cd ~/microchip/Libero_SoC_v2024.2/Libero/bin
export LM_LICENSE_FILE=<your_license_path>
./libero- Clone Repository
git clone https://github.com/cupx0j0e/EchoCore.git- Open Project in Libero
- Launch Libero
- Open the
.prjxfile (fromQAM16/libero_filesorUltrasound/libero_files)
- Explore
- Flash on your Beaglev fire fpga
OR
- Create a new project
- Adding Custom Modules
- Import
.vfiles → Files → Import HDL Source Files - Build hierarchy
- Drag & drop modules into SmartDesign
- Right-click inputs/outputs (e.g.,
clk,reset,data_out) → set as Top Module ports
- Import
- Using IP Cores
- Identify and add required IP cores
- Configure via SmartDesign pop-up
- Save and connect ports (ensure no unconnected signals)
- Simulation
- Import testbench
.vfile as Stimulus - Set SmartDesign as root in hierarchy
- Set testbench as Active Stimulus
- Run Pre-Synthesis Simulation (Verify → Simulate)
- View resultant waveforms
- Import testbench
- Synthesis & Bitstream Generation
- Run Synthesis → confirm no errors
- Open Constraints Manager → assign I/O pins → lock pins
- Run Place & Route
- Run Generate Bitstream (export under
designer/export/) - Flash onto FPGA
The project has successfully demonstrated the individual implementation of both the 16-QAM and Ultrasound pipelines on the FPGA. The core goal of achieving full parallel execution of both pipelines is the final step.
| Feature | Status |
|---|---|
| 16-QAM TX | Completed |
| Ultrasound | Completed |
| Parallelism | In Progress |
The pre-synthesis simulations for both pipelines were conducted to verify the core logic before hardware implementation. The results confirmed the functionality of each module.
16-QAM Pipeline: The simulation successfully generated the I and Q components from the input 4-bit random data stream. A post-simulation analysis of the I and Q data points in MATLAB produced the expected 16-QAM constellation diagram, confirming that the symbol mapping and modulation were implemented correctly. The output waveform demonstrated the characteristic amplitude and phase shifts, validating the design.
Ultrasound Pipeline: The simulation of the ultrasound signal chain with synthetic echo data confirmed the functionality of the processing stages. The pseudo-dynamic receive beamforming algorithm successfully focused the received echoes, producing a high-amplitude peak that verified the proper application of delay values. Subsequent processing, including envelope detection and log compression, yielded data suitable for scan conversion, which, when run through the Python script, produced the expected B-mode image.
We successfully flashed the QAM and ultrasound bitstreams on Libero. For the QAM demonstration, the output obtained through the UART was connected to an oscilloscope to obtain the corresponding waveforms. For the ultrasound demonstration, the UART data was taken and run through the scan conversion in Python to obtain the final B-mode image display.
- Implement 16-QAM on FPGA
- Implement Ultrasound signal chain
- Integrate QAM + Ultrasound in real-time (parallel pipeline)
- Test with live data and optimize latency
- Missing IP cores (Libero 2025) → Use Libero 2024.2
- Licensing errors → Verify license path
- FPGA not detected → Check USB drivers & cable connection
- SRA VJTI – EchoCore Project
- FPGA Basics Blog
- IEEE Paper on QAM16
- Implementing QAM16 on FPGA
- Ultrasound FPGA Beamformer GitHub
- A Single FPGA-Based Portable Ultrasound Imaging System for Point-of-Care Applications