Locker Security System

A digital locker security system implemented in VHDL for FPGA deployment, featuring a 3-digit hexadecimal PIN-based access control mechanism with real-time visual feedback through seven-segment displays and LED indicators.

Table of Contents

• Overview
• Features
• Supported FPGA Boards
• System Architecture
• Hardware Components
• File Structure
• Prerequisites
• Installation
• Usage Guide
• Technical Specifications
• State Machine Design
• Future Enhancements
• Contributors
• License

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Overview

This project implements a secure digital locking mechanism designed for applications such as mall lockers, gym storage units, or any facility requiring PIN-based security. The system utilizes a 3-digit hexadecimal PIN (supporting values 0-9 and A-F) with an intuitive user interface that guides users through both PIN creation and verification processes.

The design emphasizes reliability through hardware-level debouncing, visual feedback mechanisms, and a robust finite state machine (FSM) architecture that handles all user interactions and state transitions.

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Features

Feature	Description
Hexadecimal PIN Entry	3-digit PIN supporting 16 values per digit (0-9, A-F), providing 4,096 unique combinations
Visual Feedback	Real-time display on seven-segment display with distinct states for OPEN/LOCK
LED Status Indicator	Dedicated LED output indicating locker state (locked/unlocked)
Blinking Digit Selection	Currently selected digit blinks to provide clear user feedback
Hardware Debouncing	Button inputs are debounced in hardware to prevent false triggers
Asynchronous Reset	System can be reset at any time to clear all settings
Modular Design	Component-based architecture enabling easy maintenance and testing
Multi-Board Support	Pre-configured constraint files for both Nexys A7 (DDR) and Basys 3 FPGA boards

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Supported FPGA Boards

This project includes ready-to-use constraint files for two popular Digilent FPGA development boards:

Board Comparison

Feature	Nexys A7 (DDR)	Basys 3
FPGA Chip	Artix-7 XC7A100T	Artix-7 XC7A35T
Clock Frequency	100 MHz	100 MHz
Seven-Segment Digits	8 digits	4 digits
Constraint File	constr.xdc	constr_basys3.xdc
Reset Input	Push button (BTNR)	Switch (SW0)
Navigation Buttons	BTNU, BTND, BTNL	BTNU, BTND, BTNL

Pin Mapping Summary

Nexys A7 (DDR) Pin Assignments

Signal	Pin	Description
clock	E3	100 MHz system clock
up	M18	UP button (BTNU)
down	P18	DOWN button (BTND)
sel	M17	SELECT button (BTNL)
reset	P17	RESET button (BTNR)
led_lock	H17	Lock status LED (LD0)
an[7:0]	J17, J18, T9, J14, P14, T14, K2, U13	Anode controls
cat[6:0]	T10, R10, K16, K13, P15, T11, L18	Cathode segments

Basys 3 Pin Assignments

Signal	Pin	Description
clock	W5	100 MHz system clock
up	T18	UP button (BTNU)
down	U17	DOWN button (BTND)
sel	T17	SELECT button (BTNL)
reset	V17	RESET switch (SW0)
led_lock	U16	Lock status LED (LD0)
an[3:0]	U2, U4, V4, W4	Anode controls (active display)
an[7:4]	P3, N3, P1, L1	Anode controls (directly driven)
cat[6:0]	W7, W6, U8, V8, U5, V5, U7	Cathode segments

Note: The Basys 3 board has only 4 seven-segment display digits compared to 8 on the Nexys A7. The design automatically adapts, using the first 4 digits for PIN display and the remaining anode signals are directly connected to available I/O pins.

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System Architecture

The system follows a modular hierarchical design with clearly separated concerns:

                    ┌─────────────────────────────────────────┐
                    │              User Interface             │
                    │   (UP, DOWN, SEL, RESET Buttons)        │
                    └───────────────────┬─────────────────────┘
                                        │
              ┌─────────────────────────┼─────────────────────────┐
              │                         │                         │
    ┌─────────▼─────────┐    ┌──────────▼──────────┐    ┌─────────▼─────────┐
    │     Debouncer     │    │  Frequency Divider  │    │   Code Selector   │
    │     Circuits      │    │  (Visual Effects)   │    │   (Main FSM)      │
    │                   │    │                     │    │                   │
    │ - Button filtering│    │ - Clock division    │    │ - PIN storage     │
    │ - Edge detection  │    │ - Blink timing      │    │ - State control   │
    └─────────┬─────────┘    └──────────┬──────────┘    └─────────┬─────────┘
              │                         │                         │
              └─────────────────────────┼─────────────────────────┘
                                        │
                              ┌─────────▼─────────┐
                              │    SSD Driver     │
                              │                   │
                              │ - Multiplexing    │
                              │ - Cathode control │
                              │ - Display logic   │
                              └─────────┬─────────┘
                                        │
                    ┌───────────────────┴───────────────────┐
                    │                                       │
          ┌─────────▼─────────┐               ┌─────────────▼─────────────┐
          │  Seven-Segment    │               │      LED Indicator        │
          │     Display       │               │    (Lock Status)          │
          └───────────────────┘               └───────────────────────────┘

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Hardware Components

Top-Level Entity: circuit.vhd

The main circuit integrates all subcomponents and manages signal routing between modules.

Port Interface:

Port	Direction	Width	Description
up	Input	1 bit	Increment button
down	Input	1 bit	Decrement button
sel	Input	1 bit	Selection/confirm button
clock	Input	1 bit	System clock (100 MHz)
reset	Input	1 bit	Asynchronous reset
led_lock	Output	1 bit	Lock status indicator
an	Output	8 bits	Anode control for SSD
cat	Output	7 bits	Cathode control for SSD

Subcomponents

Component	File	Description
Debouncer	debouncer.vhd	Filters mechanical button bounce using a counter-based approach
Frequency Divider	frequency_divider.vhd	Divides the 100 MHz clock to create visible blinking effects
Counter	counterbun.vhd	Generic counter used by debouncer and frequency divider
D Flip-Flop	d_flipflop.vhd	Basic storage element for sequential logic
Code Selector	code_selector.vhd	Main FSM handling PIN entry, storage, and verification
SSD Controller	SSD.vhd	Manages seven-segment display multiplexing and cathode patterns

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File Structure

project_nexys/
├── project_nexys.srcs/
│   ├── sources_1/
│   │   └── src/
│   │       ├── circuit.vhd          # Top-level entity
│   │       ├── code_selector.vhd    # Main FSM logic
│   │       ├── SSD.vhd              # Seven-segment display driver
│   │       ├── debouncer.vhd        # Button debouncing circuit
│   │       ├── frequency_divider.vhd # Clock divider for visual effects
│   │       ├── counterbun.vhd       # Counter component
│   │       └── d_flipflop.vhd       # D flip-flop component
│   ├── constrs_1/
│   │   └── new/
│   │       ├── constr.xdc           # Nexys A7 (DDR) constraint file
│   │       └── constr_basys3.xdc    # Basys 3 constraint file
│   └── README.md                    # This documentation
└── Documentation Locker Security System.pdf  # Detailed project documentation

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Prerequisites

• Xilinx Vivado Design Suite (2019.1 or later recommended)
• FPGA Development Board: One of the following:
  • Digilent Nexys A7-100T (or Nexys 4 DDR)
  • Digilent Basys 3
  • Other Artix-7 based boards (requires custom constraint file)
• USB Cable: Micro-USB for programming and power supply

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Installation

1. Clone the Repository

   git clone https://github.com/username/Locker-Security-System.git
   cd Locker-Security-System

2. Open in Vivado

   • Launch Xilinx Vivado
   • Select "Open Project" or create a new project and add source files

3. Add Source Files

   • Navigate to project_nexys/project_nexys.srcs/sources_1/src/
   • Add all .vhd files to the project

4. Set Top-Level Entity

   • Right-click on circuit.vhd in the Sources panel
   • Select "Set as Top"

5. Add Constraints (Select based on your board)

   For Nexys A7 (DDR):

   • Import constrs_1/new/constr.xdc

   For Basys 3:

   • Import constrs_1/new/constr_basys3.xdc

   Important: Only add ONE constraint file to your project. Remove or disable the other constraint file if both are present.

6. Generate Bitstream

   • Run Synthesis
   • Run Implementation
   • Generate Bitstream

7. Program the FPGA

   • Connect your board via USB
   • Open Hardware Manager
   • Program the device with the generated .bit file

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Usage Guide

Button Configuration

Button	Function
UP	Increment current digit value (0 → 1 → ... → E → F → 0)
DOWN	Decrement current digit value (0 → F → E → ... → 1 → 0)
SEL	Confirm current digit and advance to next position
RESET	Clear all settings and return to initial state

Display Indicators

• "OPEN": Displayed when the locker is unlocked and ready for use
• "CLSD": Displayed when the locker is locked (closed)
• Blinking Digit: Indicates the currently active digit being modified
• LED ON: Locker is in locked state
• LED OFF: Locker is in unlocked state

Setting a PIN (First-Time Use)

1. Power on the system - display shows "OPEN"
2. Press SEL to begin PIN creation
3. The first digit position will start blinking
4. Use UP/DOWN to select the desired value (0-F)
5. Press SEL to confirm and move to the second digit
6. Repeat steps 4-5 for the second and third digits
7. After confirming the third digit, the locker locks automatically
8. LED illuminates and display shows "CLSD"

Unlocking the Locker

1. Press SEL to begin PIN entry
2. The first digit position will start blinking
3. Enter your 3-digit PIN using UP/DOWN and SEL
4. If the PIN matches:
   • Locker unlocks
   • LED turns off
   • Display shows "OPEN"
5. If the PIN is incorrect:
   • Entry resets
   • User must re-enter the complete PIN

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Technical Specifications

Parameter	Value
Clock Frequency	100 MHz (board clock)
Divided Clock	4 Hz (for blinking effects)
PIN Combinations	4,096 (16³)
Display Type	8-digit multiplexed seven-segment
Debounce Time	Approximately 10-20 ms
Reset Type	Asynchronous, active-high

Clock Division

The frequency divider creates a slower clock signal for visual effects:

Division Factor = 25,000,000
Output Frequency = 100 MHz / 25,000,000 = 4 Hz

Seven-Segment Encoding

The system uses common-anode seven-segment displays with the following cathode encoding:

Digit	Hex	Cathode Pattern (abcdefg)
0	0x0	0000001
1	0x1	1001111
2	0x2	0010010
3	0x3	0000110
4	0x4	1001100
5	0x5	0100100
6	0x6	0100000
7	0x7	0001111
8	0x8	0000000
9	0x9	0000100
A	0xA	0001000
B	0xB	1100000
C	0xC	0110001
D	0xD	1000010
E	0xE	0110000
F	0xF	0111000

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State Machine Design

The code_selector module implements a finite state machine with the following states:

Lock State Machine (Setting PIN)

State "000" → First digit entry
    ↓ (SEL pressed)
State "100" → Second digit entry
    ↓ (SEL pressed)
State "110" → Third digit entry
    ↓ (SEL pressed)
State "111" → Locked (PIN stored)

Tries State Machine (Entering PIN)

State "000" → Enter first digit
    ↓ (SEL pressed)
State "100" → Enter second digit
    ↓ (SEL pressed)
State "110" → Enter third digit
    ↓ (SEL pressed)
State "111" → Verify PIN
    ↓
If match → Unlock (return to "000")
If no match → Reset tries, retry entry

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Future Enhancements

Enhancement	Description
Hexadecimal Keypad	Direct digit entry for faster PIN input
Timeout Feature	Auto-lock after period of inactivity
Wrong PIN Counter	Lock system after multiple failed attempts
RFID Integration	Alternative access method using RFID tags
Master Override	Emergency access functionality for administrators
Haptic Feedback	Vibration motor for tactile button confirmation
Audio Feedback	Buzzer for lock/unlock confirmation sounds
Extended PIN Length	Support for 4-6 digit PINs for enhanced security

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Contributors

Name	Role
Tianu Cosmin-Nicolae	Design and Implementation
Palacian Bogdan-Tudor	Design and Implementation

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License

This project is licensed under the MIT License - see the LICENSE file for details.

This project was originally developed as part of the Digital System Design (DSD) course at the Faculty of Automation and Computer Science, Technical University of Cluj-Napoca, Romania (2023).

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Acknowledgments

• Faculty of Automation and Computer Science, TUCN
• Digital System Design course instructors and teaching assistants