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Enhance TraceEncoderController to include hartId and fix formatting i… #3764

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f82a9d4
Enhance TraceEncoderController to include hartId and fix formatting i…
iansseijelly Oct 5, 2025
bff9532
add: context into the trace core interface bundle
iansseijelly Oct 6, 2025
8efb6c1
add: make the sink target 8 wide instead of 1
iansseijelly Oct 9, 2025
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1 change: 1 addition & 0 deletions src/main/scala/rocket/RocketCore.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -847,6 +847,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)

io.trace_core_ingress.get.group(0) <> trace_ingress.io.out
io.trace_core_ingress.get.priv := csr.io.trace(0).priv
io.trace_core_ingress.get.ctx := csr.io.ptbr.asid
io.trace_core_ingress.get.tval := csr.io.tval
io.trace_core_ingress.get.cause := csr.io.cause
io.trace_core_ingress.get.time := csr.io.time
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2 changes: 1 addition & 1 deletion src/main/scala/tile/RocketTile.scala
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Expand Up @@ -92,7 +92,7 @@ class RocketTile private(
* and selecting trace sink
*/
val trace_encoder_controller = rocketParams.traceParams.map { t =>
val trace_encoder_controller = LazyModule(new TraceEncoderController(t.encoderBaseAddr, xBytes))
val trace_encoder_controller = LazyModule(new TraceEncoderController(t.encoderBaseAddr, xBytes, tileId))
connectTLSlave(trace_encoder_controller.node, xBytes)
trace_encoder_controller
}
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2 changes: 1 addition & 1 deletion src/main/scala/trace/TraceCoreIngress.scala
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Expand Up @@ -43,7 +43,7 @@ class TraceCoreIngress(val params: TraceCoreParams) extends Module {
itype := TraceItype.ITNothing
}
itype
}
}

io.out.iretire := io.in.valid
io.out.iaddr := io.in.pc
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1 change: 1 addition & 0 deletions src/main/scala/trace/TraceCoreInterface.scala
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Expand Up @@ -43,6 +43,7 @@ class TraceCoreGroup (val params: TraceCoreParams) extends Bundle {
class TraceCoreInterface (val params: TraceCoreParams) extends Bundle {
val group = Vec(params.nGroups, new TraceCoreGroup(params))
val priv = UInt(4.W)
val ctx = UInt(params.xlen.W)
val tval = UInt(params.xlen.W)
val cause = UInt(params.xlen.W)
val time = UInt(params.xlen.W)
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7 changes: 3 additions & 4 deletions src/main/scala/trace/TraceEncoderController.scala
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Expand Up @@ -21,15 +21,14 @@ class TraceEncoderControlInterface() extends Bundle {
val target = UInt(TraceSinkTarget.width.W)
val bp_mode = UInt(32.W)
}
class TraceEncoderController(addr: BigInt, beatBytes: Int)(implicit p: Parameters) extends LazyModule {
class TraceEncoderController(addr: BigInt, beatBytes: Int, hartId: Int)(implicit p: Parameters) extends LazyModule {

val device = new SimpleDevice("trace-encoder-controller", Seq("ucbbar,trace0"))
val device = new SimpleDevice(s"trace-encoder-controller$hartId", Seq("ucbbar,trace"))
val node = TLRegisterNode(
address = Seq(AddressSet(addr, 0xFF)),
device = device,
beatBytes = beatBytes
)

override lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
Expand Down Expand Up @@ -73,7 +72,7 @@ class TraceEncoderController(addr: BigInt, beatBytes: Int)(implicit p: Parameter
RegFieldDesc("impl", "Trace encoder implementation"))
),
0x20 -> Seq(
RegField(1, trace_sink_target,
RegField(8, trace_sink_target,
RegFieldDesc("target", "Trace sink target"))
),
0x24 -> Seq(
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