GitHub - charan-akula/Timing-violation-using-ML: Developed an ML system to predict timing violations in VLSI RTL designs using gate-level features. Trained a decision tree on synthesized RTL data for early-stage violation detection.The approach enhances design reliability, reduces costly iterations, and minimizes late-stage failures and speeds up development cycles.

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Developed an ML system to predict timing violations in VLSI RTL designs using gate-level features. Trained a decision tree on synthesized RTL data for early-stage violation detection.The approach enhances design reliability, reduces costly iterations, and minimizes late-stage failures and speeds up development cycles.