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Unable to verify my Rapidsmith installation

Status: Open.

#387 In byuccl/RapidSmith2;

· sandeeprpandey opened on May 8, 2020

Resolve duplication of efforts with Lut Routethroughs and Pseudo VCC Pins

Status: Open.

#385 In byuccl/RapidSmith2;

· DallonTG opened on Aug 27, 2019

Get 7 Series bonded sites with true site names

enhancement

Status: Open.

#376 In byuccl/RapidSmith2;

· DallonTG opened on Jun 5, 2019

PartialDeviceTest Failing with OpenJDK 11

Status: Open.

#375 In byuccl/RapidSmith2;

· DallonTG opened on Jun 5, 2019

Include common hidden macros in Cell Library

enhancement

Status: Open.

#370 In byuccl/RapidSmith2;

· DallonTG opened on Mar 4, 2019

Create EDIF RPMs for all macros

Status: Open.

#367 In byuccl/RapidSmith2;

· DallonTG opened on Feb 6, 2019

Travis CI build info missing

Status: Open.

#366 In byuccl/RapidSmith2;

· DallonTG opened on Jan 26, 2019

RapidSmith2 support for Virtex UltraScale+ XCVU9P-L2FLGA2104 Device

Status: Open.

#353 In byuccl/RapidSmith2;

· amitkulkarnis opened on Aug 16, 2018

Net properties not included in EDIF

bug

Status: Open.

#352 In byuccl/RapidSmith2;

· DallonTG opened on May 17, 2018

Role of RS2 and RapidWright

Status: Open.

#347 In byuccl/RapidSmith2;

· trharoldsen opened on May 2, 2018

reverseRouting naming inconsistency

Status: Open.

#343 In byuccl/RapidSmith2;

· DallonTG opened on Mar 3, 2018

Carry4 CI cell pin maps to CYINIT pin and not CI pin on BEL.

Priority:High

Status: Open.

#339 In byuccl/RapidSmith2;

· trharoldsen opened on Feb 18, 2018