Hi, I’m Sriram Vaibhav 👋
ECE undergrad at IIIT Nagpur | VLSI & FPGA enthusiast | Currently interning at ISRO, working on digital comms and hardware design 🚀 | Skills: Verilog, SystemVerilog, C, C++, Python.
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NRSC, ISRO
- Hyderabad
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14:07
(UTC +05:30) - in/sriramvaibhav
- vaibhav.hehe
- https://vaibhavheh.vercel.app/
Popular repositories Loading
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Zero-Crossing-Error-Timing-Detection
Zero-Crossing-Error-Timing-Detection PublicZero-crossing based symbol synchronization technique for timing error detection in digital communication systems.
Verilog 3
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PAR_UniqueWord
PAR_UniqueWord PublicThis project implements a digital communication system component designed to resolve phase ambiguity in Quadrature Phase Shift Keying (QPSK) signals. Phase ambiguity is a common issue in QPSK syste…
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Phase-Ambiguity-Resolver-using-Differential-Decoding
Phase-Ambiguity-Resolver-using-Differential-Decoding PublicPhase ambiguity in QPSK arises because the carrier can lock with 0°, 90°, 180°, or 270° rotation, causing bit errors. Differential decoding solves this by encoding data in the phase difference betw…
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Viterbi-Decoder-213
Viterbi-Decoder-213 PublicVerilog implementation of the Viterbi decoding algorithm. This decoder is designed for efficient error correction in digital communication systems. This includes Branch Metric Unit, Path Metric Uni…
Verilog 2
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Reed-Solmon-Decoding
Reed-Solmon-Decoding PublicVerilog implementation of the Reed Solmon decoding algorithm, comprising of the blocks , "SYNDROME", "CHEIN SEARCH", "BERLEYKEMP", and "FORNEY".
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