This homework consists in writing a simulator of a simple out-of-order processor called OoO470. The processor runs a minimal subset of the RISC-V instruction set and is implemented with internal data structures similar to the MIPS R10000, studied in Lab #1. The simulation is meant to be cycle-exact and must update the internal data structures precisely as the real processor. The simulator reads an assembly program; it dumps the internal data structures at the end of every cycle until the complete execution terminates.
please go to /hw1/ for my implementation