Digital Design & Verification Engineer | BSc in EEE (UIU, 2024) | Designed RISC-V Processor, Skilled in SystemVerilog, Verilog, and UVM.
-
United International University
- Dhaka, Bangladesh
- in/ashrafulbhuiyan2
Popular repositories Loading
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.