Name		Name	Last commit message	Last commit date
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Layered Testbench		Layered Testbench
16-bit_CLA_Report.pdf		16-bit_CLA_Report.pdf
README.md		README.md
design.sv		design.sv

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16-bit Carry Lookahead Adder

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A hierarchical 16-bit Carry Lookahead Adder is designed in Cadence using system verilog language, verified with directed and layered testbench and optimized for power, performance, and area (PPA)

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SystemVerilog 100.0%