The LogicCard is a compact and affordable FPGA development board featuring the Renesas SLG47910V FPGA with integrated USB programming via a CH552 microcontroller. The board includes an 11-pin Charlieplexed LED matrix (15×7 LEDs) and 4 user buttons, making it ideal for portable FPGA demonstrations and learning projects. The resistors for the LED matrix can be desoldered and the test points can be used for external applications.
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FPGA: Renesas SLG47910V (24-pin STQFN)
- 1120 5-bit Look-Up Tables (LUTs)
- 1120 D-type Flip-Flops (DFFs)
- 5 kb distributed SRAM
- 32 kb embedded Block RAM (BRAM)
- 19 GPIOs available
- 50 MHz on-chip oscillator
- Phase-Locked Loop (PLL)
- Advanced 6-input 2-output lookup table (LUT) structure for increased efficiency in high-usage designs
- Low price that opens the low-density FPGA market to customers of all sizes (50 Cents at high volume)
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USB Programming: CH552 microcontroller implementing serprog protocol
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Configuration Storage: External SPI NOR Flash (W25Q80DVSNIG - 1 Mbit)
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User Interface: 15×7 LED matrix (105 LEDs) using 11 GPIO pins + 4 buttons
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Power: USB-powered with dual LDO regulation (5V → 3.3V → 1.1V)
| Pin | Name | Description | Net |
|---|---|---|---|
| 1 | GPIO10 | General Purpose I/O | CHRLY_2 |
| 2 | GPIO11 | General Purpose I/O | CHRLY_3 |
| 3 | GPIO12 | General Purpose I/O | CHRLY_4 |
| 4 | GPIO13 | General Purpose I/O | CHRLY_5 |
| 5 | GPIO14 | General Purpose I/O | CHRLY_6 |
| 6 | GPIO15 | General Purpose I/O | CHRLY_7 |
| 7 | GPIO16 | General Purpose I/O | CHRLY_8 |
| 8 | GPIO17 | General Purpose I/O | CHRLY_9 |
| 9 | GPIO18 | General Purpose I/O | CHRLY_10 |
| 10 | EN(nSLEEP) | Enable / Sleep (active low) | FPGA_EN |
| 11 | PWR(nRST) | Power / Reset (active low) | FPGA_RST |
| 12 | GND | Ground | GND |
| 13 | GPIO0 | General Purpose I/O | BUTTON_1 |
| 14 | GPIO1 | General Purpose I/O | BUTTON_2 |
| 15 | GPIO2 | General Purpose I/O | BUTTON_3 |
| 16 | GPIO3/SPI_CLK | GPIO 3 / SPI Clock | SPI_SCK |
| 17 | GPIO4/SPI_SS | GPIO 4 / SPI Chip Select | SPI_CS |
| 18 | GPIO5/SPI_SI | GPIO 5 / SPI Slave In | SPI_MISO |
| 19 | GPIO6/SPI_SO | GPIO 6 / SPI Slave Out | SPI_MOSI |
| 20 | GPIO7 | General Purpose I/O | BUTTON_4 |
| 21 | VDDIO | I/O Supply Voltage | +3.3V |
| 22 | VDDC | Core Supply Voltage | +1.1V |
| 23 | GPIO8 | General Purpose I/O | CHRLY_0 |
| 24 | GPIO9 | General Purpose I/O | CHRLY_1 |
| Pin | Name | Description | Net |
|---|---|---|---|
| 1 | V33 | Internal USB power regulator | +3.3V |
| 2 | MOSI/PWM1/TIN3 | Port 1.5 | SPI_MOSI |
| 3 | T2_/CAP1_/SCS | Port 1.4 | SPI_CS |
| 4 | TXD1_/INT0/VBUS1 | Port 3.2 | LED |
| 5 | MISO/RXD1/TIN4 | Port 1.6 | SPI_MISO |
| 6 | SCK/TXD1/TIN5 | Port 1.7 | SPI_SCK |
| 7 | RST/T2EX_/CAP2_ | Reset | Reset |
| 8 | T2/CAP1/TIN0 | Port 1.0 | FPGA_RST |
| 9 | PWM2_/TXD | Port 3.1 | NC |
| 10 | PWM1_/RXD | Port 3.0 | NC |
| 11 | T2EX/CAP2/TIN1 | Port 1.1 | NC |
| 12 | INT1 | Port 3.3 | FPGA_EN |
| 13 | PWM2/RXD1_/T0 | Port 3.4 | NC |
| 14 | UDP | Port 3.6 | USB_D+ |
| 15 | UDM | Port 3.7 | USB_D- |
| 16 | VCC/VDD | Power | +3.3V |
| 17 | GND/VSS | GND | GND |
| Pin | Name | Description | Net |
|---|---|---|---|
| 1 | /CS | Chip Select (active low) | SPI_CS |
| 2 | DO(IO1) | Data Out / I/O 1 | SPI_MISO |
| 3 | /WP(IO2) | Write Protect (active low) / I/O 2 | Pull-up +3.3V |
| 4 | GND | Ground | GND |
| 5 | DI(IO0) | Data In / I/O 0 | SPI_MOSI |
| 6 | CLK | Clock | SPI_SCK |
| 7 | /HOLD(IO3) | Hold (active low) / I/O 3 | Pull-up +3.3V |
| 8 | VCC | Supply Voltage | +3.3V |
| FPGA GPIO | FPGA Pin | Matrix Pin | Function |
|---|---|---|---|
| GPIO8 | 23 | CHRLY_1 | Charlieplex Pin 1 |
| GPIO9 | 24 | CHRLY_2 | Charlieplex Pin 2 |
| GPIO10 | 1 | CHRLY_3 | Charlieplex Pin 3 |
| GPIO11 | 2 | CHRLY_4 | Charlieplex Pin 4 |
| GPIO12 | 3 | CHRLY_5 | Charlieplex Pin 5 |
| GPIO13 | 4 | CHRLY_6 | Charlieplex Pin 6 |
| GPIO14 | 5 | CHRLY_7 | Charlieplex Pin 7 |
| GPIO15 | 6 | CHRLY_8 | Charlieplex Pin 8 |
| GPIO16 | 7 | CHRLY_9 | Charlieplex Pin 9 |
| GPIO17 | 8 | CHRLY_10 | Charlieplex Pin 10 |
| GPIO18 | 9 | CHRLY_11 | Charlieplex Pin 11 |
| Button | FPGA GPIO | FPGA Pin |
|---|---|---|
| BUTTON_1 | GPIO0 | 13 |
| BUTTON_2 | GPIO1 | 14 |
| BUTTON_3 | GPIO2 | 15 |
| BUTTON_4 | GPIO7 | 20 |
The SLG47910V is configured to use External SPI Flash Mode (SPI Master):
- FPGA acts as SPI Master during configuration
- External SPI Flash (W25Q80) acts as SPI Slave
- GPIO4 (SPI_SS) has a 10kΩ pull-up ensuring HIGH at power-up
Typical Operation Sequence:
- MCU asserts FPGA_RST to hold FPGA in reset
- MCU takes control of SPI bus and writes configuration data to Flash
- MCU releases FPGA_RST
- FPGA boots and reads configuration from the same SPI Flash
- FPGA becomes operational
- Required: 384 kbit (48 KB) for full configuration
- Available: 1 Mbit (128 KB) in W25Q80 Flash
The 15×7 LED matrix (105 LEDs) is controlled using 11 GPIO pins via Charlieplexing:
Formula:
Maximum LEDs = n × (n - 1)
With 11 pins: 11 × 10 = 110 possible LEDs
Actual usage: 105 LEDs (15 rows × 7 columns)
Each Charlieplex pin should have a series resistor (82Ω) for current limiting:
- Forward voltage (VF): ~1.8V (yellow LEDs)
- Forward current (IF): ~10 mA for visibility
- These resistors can be desoldered to use test points for external applications
- As one GPIO drives the anode and another the cathode, the total resistance is 2 × 82Ω = 164Ω
The CH552 firmware implements the serprog protocol for flashrom compatibility:
Supported Features:
- SPI Master interface
- FPGA reset/enable control with bus arbitration
- Visual LED feedback during programming operations
- Compatible with standard flashrom tool
USB Identifiers:
- Vendor ID: 0x1a86 (WCH)
- Product ID: 0x5722
- Device Class: CDC
- Product String: "ch552-serprog"
LED Behavior:
- On during power-up and USB enumeration
- Blinks during USB configuration
- Off when idle and ready for commands
- On during flash programming operations (CH552 controls SPI bus)
- Off when FPGA is enabled (FPGA controls SPI bus)
# Flash FPGA bitstream using flashrom
flashrom -p serprog:dev=/dev/ttyACM0 -w FPGA_bitstream_FLASH_MEM.bin
# Read current configuration
flashrom -p serprog:dev=/dev/ttyACM0 -r current_config.bin
# Erase flash
flashrom -p serprog:dev=/dev/ttyACM0 -EThe project includes two ready-to-use FPGA bitstreams:
- Location: examples/blink/
- Description: Simple LED blinking demo using Charlieplex configuration
- Features: Single LED blinking at 2Hz using 2 GPIO pins
- Bitstream: examples/blink/ffpga/build/bitstream/FPGA_bitstream_FLASH_MEM_1MB.bin
- Location: examples/demo/demo.ffpga
- Description: Full 15×7 LED matrix with ripple effect animation
- Features:
- 105-LED Charlieplexed matrix (15 rows × 7 columns)
- Button controls for pattern inversion, speed control, and pause/play
- Uses all 11 Charlieplex GPIO pins
- Bitstream: examples/demo/ffpga/build/bitstream/FPGA_bitstream_FLASH_MEM_1MB.bin
LogicCard/
├── hardware/ # Hardware design files
│ ├── BOM.csv # Bill of Materials
│ ├── Schematic.pdf # Circuit schematic
│ ├── 3D.step # 3D model (STEP format)
│ └── Render.png # 3D render preview
├── firmware/ # CH552 firmware source code
│ ├── ch552_serprog/ # serprog protocol implementation
│ │ └── main.c # Main firmware source
│ ├── include/ # Shared header files
│ └── build/ # Compiled firmware binaries
│ └── ch552-serprog.bin
├── examples/ # Example FPGA projects
│ ├── blink/ # Simple LED blink example
│ │ ├── blink.ffpga # GoConfigure project file
│ │ └── ffpga/ # FFPGA build artifacts
│ │ ├── src/ # Verilog source files
│ │ │ └── blink.v
│ │ └── build/ # Build output directory
│ │ └── bitstream/
│ │ ├── FPGA_bitstream_FLASH_MEM.bin (48KB)
│ │ └── FPGA_bitstream_FLASH_MEM_1MB.bin (1MB padded)
│ └── demo/ # LED matrix demo with ripple effect
│ ├── demo.ffpga # GoConfigure project file
│ └── ffpga/ # FFPGA build artifacts
│ ├── src/ # Verilog source files
│ │ └── demo.v
│ └── build/ # Build output directory
│ └── bitstream/
│ ├── FPGA_bitstream_FLASH_MEM.bin (48KB)
│ └── FPGA_bitstream_FLASH_MEM_1MB.bin (1MB padded)
└── docs/ # Documentation and datasheets
├── CH552.PDF # CH552 microcontroller datasheet
├── SLG47910.pdf # SLG47910V FPGA datasheet
├── W25Q80DV.pdf # W25Q80 Flash memory datasheet
└── LogicCard.gif # Demo animation
- Connect LogicCard to computer via USB-C cable
- The board should enumerate as a USB device
The CH552 microcontroller needs to be programmed with the serprog firmware on first use.
# Install from cargo (Rust package manager)
cargo install wchisp
# Set udev rules for non-root access
sudo tee /etc/udev/rules.d/50-wchisp.rules > /dev/null <<EOF
SUBSYSTEM=="usb", ATTRS{idVendor}=="4348", ATTRS{idProduct}=="55e0", MODE="0666"
EOF
sudo udevadm control --reload-rulesArch Linux:
yay -S wchisp- Hold the BOOT button and connect the board to your computer
- Flash the firmware:
wchisp flash firmware/build/ch552-serprog.bin
- Disconnect and reconnect the board (without holding BOOT)
- The board should now appear as
/dev/ttyACM0
For more details on wchisp, see the official repository.
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Install flashrom:
sudo apt install flashrom
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Flash one of the ready-to-use examples:
# Blink example flashrom -p serprog:dev=/dev/ttyACM0 -w examples/blink/ffpga/build/bitstream/FPGA_bitstream_FLASH_MEM_1MB.bin # Or the full LED matrix demo flashrom -p serprog:dev=/dev/ttyACM0 -w examples/demo/ffpga/build/bitstream/FPGA_bitstream_FLASH_MEM_1MB.bin
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The FPGA automatically configures and runs after programming
- Create your design using Renesas GoConfigure tool
- Generate bitstream file (
.bin) - Pad the bitstream to 1MB (flashrom requires full chip-size images):
# Pad bitstream to match W25Q80 flash size (1MB) cp FPGA_bitstream_FLASH_MEM.bin FPGA_bitstream_FLASH_MEM_1MB.bin truncate -s 1M FPGA_bitstream_FLASH_MEM_1MB.bin - Flash using:
flashrom -p serprog:dev=/dev/ttyACM0 -w FPGA_bitstream_FLASH_MEM_1MB.bin
Note: The FPGA only uses the first 48KB (384 kbit) of the flash for configuration. The W25Q80 flash chip is 1MB (1,048,576 bytes), so flashrom requires the image to be padded to the full chip size.
| Parameter | Value |
|---|---|
| FPGA Logic | 1120 LUTs, 1120 DFFs |
| Memory | 5kb SRAM + 32kb BRAM |
| I/O Pins | 19 GPIOs |
| Clock | 50 MHz internal oscillator + PLL |
| Flash Storage | 1 Mbit SPI NOR (W25Q80) |
| USB Interface | Full Speed (12 Mbps) |
| LED Matrix | 15×7 (105 LEDs) |
| User Buttons | 4 |
| Power | USB 5V → 3.3V (TLV70233) → 1.1V (TLV74311) |
| Voltage Regulators | TLV70233DBVR (3.3V), TLV74311PDBVR (1.1V) |
| Programming | serprog/flashrom compatible |
This is an open-source hardware project. Contributions, suggestions, and feedback are welcome!
- Report issues or suggest features via GitHub Issues
- Submit pull requests for improvements
- Help improve documentation
- SLG47910V Datasheet - Renesas FPGA
- W25Q80DV Datasheet - Flash Memory
- CH552 Datasheet - USB MCU
- GoConfigure: Official Renesas FPGA development tool
- flashrom: Open-source flash programmer
- SDCC: Small Device C Compiler for CH552
- ch552_serprog - CH552 serprog implementation
- Charlieplexing Examples - LED matrix control
- LogicCard-VHDL - VHDL synthesis workflow using GHDL/Yosys for those who prefer VHDL over Verilog
This project is licensed under the CERN Open Hardware Licence Version 2 - Weakly Reciprocal (CERN-OHL-W). See the LICENSE file for full details.
- Renesas for providing SLG47910V FPGA samples and development tools
- ieiao for the CH552 serprog implementation
- ch32-rs team for the wchisp tool
- The open-source hardware and FPGA community
For questions, issues, or suggestions: