Greetings! 👋 I'm Alessandro Rivitti, a dedicated PhD student immersed in the intricate realm of Electronic Engineering. 🌐 My primary focus lies in the creation of efficient and lightning-fast FPGA hardware designs tailored for SmartNICs packet processing tasks. 💻✨

• Languages: Proficient in VHDL and Verilog, I wield the power of code to shape digital landscapes.

• Hardware Platforms: Experienced with Alveo U50, NETFPGA, RF-SOC, and ZedBoard, I've navigated a variety of hardware terrains.

• Environment: Comfortably operating in the Linux environment, I thrive in the world of open-source possibilities.

• Neural Networks: Beyond hardware, I've delved into the realm of AI, crafting Neural Networks in Python and also porting them using the FINN framework for FPGA acceleration.

When not deciphering the language of circuits, you'll find me pursuing other passions:

• Analog Photography 📷: Freezing moments in the timeless charm of film.

• Electronic Music 🎶: Grooving to the beats of circuits and melodies.

• Climbing 🧗‍♂️: Scaling heights, both in the lab and on the rocks.

Feel free to connect and discuss anything from FPGA intricacies to the beauty of analog photography! Let's explore the intersections of technology, art, and adventure. 🌟

If you have ideas to share, collaboration proposals, or just want to chat about FPGA designs, neural networks, analog photography, or climbing escapades, feel free to reach out. Looking forward to connecting with fellow enthusiasts! 🚀

Thanks for stopping by! 🌈✨

README page done using ChatGPT, I kinda agree with it but I would have definitely been way more boring than that.