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alebal123bal/README.md

Hi, I'm Alessandro

I'm an engineer working across FPGA design, embedded computer vision, and machine learning acceleration.
I build end‑to‑end systems that connect sensors, hardware pipelines, and software tooling.

My work spans:

  • FPGA-based computer vision (camera → DDR → HDMI/USB pipelines)
  • Embedded ML (YOLO, quantized inference, on‑device CV)
  • Real-time robotics tooling and simulation
  • High-performance Python systems (optimization, backtesting)
  • Hardware architecture (TL-Verilog, RISC-V educational cores)

What I Work On

  • FPGA architectures for real-time perception
  • Embedded ML deployment on constrained systems
  • Vision pipelines and UAV autonomy
  • High-performance Python tooling
  • Hardware design clarity, testing, and structure

Interests

  • FPGA design for high-throughput pipelines
  • Hardware acceleration (vision + ML)
  • Trading systems & HFT infrastructure
  • Drones & autonomous systems
  • Low-latency, deterministic compute
  • Optimization algorithms

Contact

LinkedIn: https://www.linkedin.com/in/alessandro-balzan-b024a9250
Email: balzanalessandro2001@gmail.com

Thanks for visiting my profile.

Pinned Loading

  1. Gowin_FPGA_CV Gowin_FPGA_CV Public

    Computer vision hardware acceleration using Gowin Tang Primer 20k FPGA

    Verilog 6

  2. luckfox_UAV_detection luckfox_UAV_detection Public

    Real-time drone detection @ blazing fast 20 FPS on RV1106 | Zero-copy DMA + hardware RGA acceleration | YOLOv5 RKNN | MAVLink telemetry streaming

    C++ 12 4

  3. BayesOpt_smart BayesOpt_smart Public

    Lightweight and Optimized Bayesian Optimization module

    Jupyter Notebook 1

  4. AdaBoost_smart AdaBoost_smart Public

    Leverage a mathematical trick to speedup classical AdaBoost algorithm. See the ReadMe for full details.

    Python 1

  5. ViolaJones_CUSTOM ViolaJones_CUSTOM Public

    Viola Jones train and inference custom implementation

    Jupyter Notebook 1

  6. RISCV_CPU_TL_verilog RISCV_CPU_TL_verilog Public

    Forked from stevehoover/LF-Building-a-RISC-V-CPU-Core

    Fork of the repo https://github.com/stevehoover/LF-Building-a-RISC-V-CPU-Core.git

    TL-Verilog