This is a minimalist 4-bit nano processor designed for educational and experimental use. It demonstrates the basics of CPU architecture using a simplified instruction set and core components implemented in VHDL.
- 4-bit Data Width – Lightweight processor for small-scale computation
- Core Instructions:
ADD– Performs 4-bit additionMOVE– Transfers data between registersNEGATION– Computes the two’s complement of a valueJUMP IF ZERO– Conditional jump based on zero flag
- Implemented Components:
- Register Bank
- ALU (Arithmetic Logic Unit)
- Instruction Decoder
- Slow Clock Generator
- Testbench for simulation
| File/Module | Description |
|---|---|
register_bank.vhd |
Stores values in multiple 4-bit registers |
alu.vhd |
Handles arithmetic operations |
instruction_decoder.vhd |
Decodes binary instructions |
clock_gen.vhd |
Slow clock generator for simulation timing |
cpu_top.vhd |
Top-level integration of CPU components |
testbench.vhd |
Simulates CPU behavior for testing |
- CPU architecture learning
- Instruction set experimentation
- Digital design education using VHDL
- Foundation for building more complex processors
To simulate the processor:
- Clone the repository.
- Open the project in your VHDL simulator (ModelSim, GHDL, etc.).
- Compile all VHDL files.
- Run
Nanoprocessor.vhdto observe functionality.
This project is open-source and free to use for educational purposes.
Created by,
- Lahiru Dilshan
- Thilokya Angeesa
- Sandaru Vidushan
- Sandeni Vithanage
This is Version v1.0.0. Future versions may add further instructions and functionality (like branching, memory, or extended instructions).