Fix for issue #78: Resolve Vivado conflicting register initialization…

[y-farhadi]

Fixes #78

Warnings in axixbar.v

[Synth 8-11375] Found 'W3_ARBITRATE_WRITE_REQUESTS[0].mwgrant_reg' register with conflicting initialization ["./wb2axip/rtl/axixbar.v":1194]
[Synth 8-11375] Found 'R3_ARBITRATE_READ_REQUESTS[0].mrgrant_reg' register with conflicting initialization ["./wb2axip/rtl/axixbar.v":1375]
[Synth 8-11375] Found 'W7_COUNT_PENDING_WRITES[0].mwfull_reg' register with conflicting initialization ["./wb2axip/rtl/axixbar.v":1978]
[Synth 8-11375] Found 'R7_COUNT_PENDING_READS[0].mrfull_reg' register with conflicting initialization ["./wb2axip/rtl/axixbar.v":2062]
[Synth 8-11375] Found 'W7_COUNT_PENDING_WRITES[0].mwempty_reg' register with conflicting initialization ["./wb2axip/rtl/axixbar.v":1977]
[Synth 8-11375] Found 'R7_COUNT_PENDING_READS[0].mrempty_reg' register with conflicting initialization ["./wb2axip/rtl/axixbar.v":2061]
[Synth 8-11375] Found 'W6_WRITE_RETURN_CHANNEL[0].berr_valid_reg' register with conflicting initialization ["./wb2axip/rtl/axixbar.v":1836]
[Synth 8-11375] Found 'R7_COUNT_PENDING_READS[0].rerr_none_reg' register with conflicting initialization ["./wb2axip/rtl/axixbar.v":2097]
[Synth 8-11375] Found 'R7_COUNT_PENDING_READS[0].rerr_last_reg' register with conflicting initialization ["./wb2axip/rtl/axixbar.v":2096]

These are Vivado synthesis warnings about registers in the axixbar.v (AXI crossbar from wb2axip) having conflicting initialization values. This is a known issue with the wb2axip library.

The warnings are caused by conflicting initial values in the wb2axip Verilog code. The pattern is:

initial mwgrant[N] = 0;      // Line 1189 - initial block sets to 0
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
    mwgrant[N] <= 0;         // Line 1194 - reset sets to 0 (but Vivado sees potential conflict)

In Verilog/SystemVerilog for Xilinx FPGAs, you can do this similarly to VHDL by using inline initialization instead of a separate initial block. I applied the same method.

reg mwgrant = 1'b0;       // Inline initialization at declaration

always @(posedge clk)
    if (!resetn)
        mwgrant <= 1'b0;  // Reset
    else
        mwgrant <= ...;

I tested it by adding changes to Vivado and synthesize it again in a project. It worked fine.