Path replication tool

[clavin-xlnx]

This is a tool that extracts a timing path from a design and recreates it in a new empty design. It reproduces the netlist hierarchy sufficiently to keep the same names of cells and nets. It also reproduces any clock nets involved in the timing path. This is useful for creating slimmed down test cases.

[eddieh-xlnx]

I'm seeing this for output.dcp:

report_route_status
Design Route Status
                                               :      # nets :
   ------------------------------------------- : ----------- :
   # of logical nets.......................... :          27 :
       # of nets not needing routing.......... :          20 :
           # of internally routed nets........ :          19 :
           # of nets with no loads............ :           1 :
       # of routable nets..................... :           7 :
           # of fully routed nets............. :           6 :
       # of nets with routing errors.......... :           1 :
           # of nets with some unrouted pins.. :           1 :
           # of nets with antennas/islands.... :           1 :
   ------------------------------------------- : ----------- :


Nets with Routing Errors:
  base_mb_i/clk_wiz_1/inst/clk_out1
    Antenna Nodes: XIPHY_L_X32Y120/CLK_BUFGCE_92_CLK_OUT

Selected (white) node is the antenna node above -- looks like you're missing some intra-site routing?

---

Overall, I think this is a really helpful utility and has potential in lots of areas. We might need to talk about the exact use case you've built this for to see if any more features are required/warranted.

[eddieh-xlnx]

If you want to gate the whole test, I would use:

Assumptions.assumeTrue(FileTools.isVivadoOnPath());

instead so that this test comes up as "skipped" rather than as "passed".

Otherwise, I think there's still some value in running the class here without checking it with Vivado, so perhaps you don't need any gating since assertFullyRouted() gates already.

[eddieh-xlnx]

I think PathExtractor is a better name for this class, since replicate could be taken as in-place replication?

[eddieh-xlnx]

Does this only work for a single path? or does it work for a list of pins (which could represent no paths (completely disjoint), a single path, or many disjoint or non-disjoint paths?)

[eddieh-xlnx]

You're invoking the router to route all unrouted pins. That seems to be an overkill, and could cause pins that failed to be copied above to show up as routed which could be dangerous.

I think your thought process here is that CE/SR pins connected to VCC must be unambiguously routed, and so there's no harm in re-routing it? If so, I think it would more efficient/less risky if you were to call GlobalSignalRouting.routeStaticNet() directly.

[clavin-xlnx]

Is there an example of how to use GlobalSignalRouting.routeStaticNet() without using RWRoute? It also seems like I need to identify the SitePinInst objects explicitly.

[clavin-xlnx]

I'm seeing this for output.dcp:

report_route_status
Design Route Status
                                               :      # nets :
   ------------------------------------------- : ----------- :
   # of logical nets.......................... :          27 :
       # of nets not needing routing.......... :          20 :
           # of internally routed nets........ :          19 :
           # of nets with no loads............ :           1 :
       # of routable nets..................... :           7 :
           # of fully routed nets............. :           6 :
       # of nets with routing errors.......... :           1 :
           # of nets with some unrouted pins.. :           1 :
           # of nets with antennas/islands.... :           1 :
   ------------------------------------------- : ----------- :


Nets with Routing Errors:
  base_mb_i/clk_wiz_1/inst/clk_out1
    Antenna Nodes: XIPHY_L_X32Y120/CLK_BUFGCE_92_CLK_OUT

Very strange, it passes clean in my sandbox and when I load the DCP into Vivado, it is fully routed.

I've tried in a different sandbox and it also exhibits the error you have described so I'll have to investigate what is the difference.

[clavin-xlnx]

I'm seeing this for output.dcp:

report_route_status
Design Route Status
                                               :      # nets :
   ------------------------------------------- : ----------- :
   # of logical nets.......................... :          27 :
       # of nets not needing routing.......... :          20 :
           # of internally routed nets........ :          19 :
           # of nets with no loads............ :           1 :
       # of routable nets..................... :           7 :
           # of fully routed nets............. :           6 :
       # of nets with routing errors.......... :           1 :
           # of nets with some unrouted pins.. :           1 :
           # of nets with antennas/islands.... :           1 :
   ------------------------------------------- : ----------- :


Nets with Routing Errors:
  base_mb_i/clk_wiz_1/inst/clk_out1
    Antenna Nodes: XIPHY_L_X32Y120/CLK_BUFGCE_92_CLK_OUT

Very strange, it passes clean in my sandbox and when I load the DCP into Vivado, it is fully routed.

I've tried in a different sandbox and it also exhibits the error you have described so I'll have to investigate what is the difference.

Ok, it looks like with Vivado 2025.1, the result is interpreted as fully routed. However, with 2025.2, it gives the result you shared above. Digging into it further, there was a site wire on the BUFGCE that was not populated. Apparently, 2025.1 is more forgiving than 2025.2. I've fixed that issue but now it also flags other antennas where clock pins are going to unused SitePinInsts. I will have to devise a new solution to work around those.