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Fixes an issue with PBlock creation on Versal where IRI_QUAD_ODD and IRI_QUAD_EVEN were treated as different ranges. Also fixes a bug where the unique structure of IRI_QUADs prevented the IRI_QUAD PBlockRange from being moved correctly. Adds a test case to ensure these changes work.

Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>
Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>
Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>
@abutt-amd abutt-amd requested a review from clavin-xlnx December 8, 2025 22:16
Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>
Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>
@clavin-xlnx clavin-xlnx merged commit a7f80f9 into Xilinx:master Dec 9, 2025
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2 participants