Array Builder Tool - Replicate Optimized Kernels in an Array #1163

clavin-xlnx · 2025-04-10T21:42:09Z

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Signed-off-by: Chris Lavin <chris.lavin@amd.com>

…ray_builder Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

…ray_builder Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

#1291) * Add ability for PerformanceExplorer to ensure external routability with InlineFlopTools Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add ability to place flip-flops around array in array_builder to make out_of_context designs more realistic Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add automatic PBlock selection and allow 5 inline flip-flops to be placed in a slice Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add option to specify whether ArrayBuilder design in OOC Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Refactor getNetsWithOverlappingNodes Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Fix java 8 compat Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Address comments Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Swap order of SLICE and DSP checks Co-authored-by: Chris Lavin <chris.lavin@amd.com> Signed-off-by: Andrew Butt <andrew.butt@amd.com> * Prevent flops from being added to the clock on fully ooc designs (no ibuf on clock) Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> --------- Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> Signed-off-by: Andrew Butt <andrew.butt@amd.com> Co-authored-by: Andrew Butt <abutt@amd.com> Co-authored-by: Chris Lavin <chris.lavin@amd.com>

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>

…to 2.20.0 (#1306) * Testing updated 3rd party packages Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Minor additions to DesignComparator Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Update license to reflect new/updated packages Signed-off-by: Chris Lavin <chris.lavin@amd.com> * rc1 jar Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix failing DesignComparator test. Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Address review comments Signed-off-by: Chris Lavin <chris.lavin@amd.com> --------- Signed-off-by: Chris Lavin <chris.lavin@amd.com>

* [ECOTools] disconnectNet() to use skipUnrouteIntraSite property Full property: rapidwright.ecotools.disconnectNet.skipUnrouteIntraSite Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Fix comment Signed-off-by: Eddie Hung <eddie.hung@amd.com> * [TestCell] Add testGetAllCorrespondingSitePinNamesLUTRouteThru() Signed-off-by: Eddie Hung <eddie.hung@amd.com> --------- Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

* Full TCL parser for XDC Signed-off-by: Jakob Wenzel <wenzel@rs.tu-darmstadt.de> * Testing updated 3rd party packages Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Minor additions to DesignComparator Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Update license to reflect new/updated packages Signed-off-by: Chris Lavin <chris.lavin@amd.com> * rc1 jar Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix failing DesignComparator test. Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Adds Jacl 1.4.1 as a library dependency Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Address review comments Signed-off-by: Chris Lavin <chris.lavin@amd.com> * add more jacadoc, refactor to own package Signed-off-by: Jakob Wenzel <wenzel@rs.tu-darmstadt.de> * 2025.2.0-rc2 jar with refactored XDCParser reference in Design.writeCheckpoint() Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Add vertical clock spine printing and clock root detection (#1314) * Add vertical clock spine printing and clock root detection Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Update comments Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add test for findClockRootVRoute Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Update test/src/com/xilinx/rapidwright/design/TestNetTools.java Co-authored-by: Chris Lavin <chris.lavin@amd.com> Signed-off-by: Andrew Butt <andrew.butt@amd.com> * Update test/src/com/xilinx/rapidwright/design/TestNetTools.java Co-authored-by: Chris Lavin <chris.lavin@amd.com> Signed-off-by: Andrew Butt <andrew.butt@amd.com> --------- Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> Signed-off-by: Andrew Butt <andrew.butt@amd.com> Co-authored-by: Chris Lavin <chris.lavin@amd.com> * Apply suggestions from code review Co-authored-by: Chris Lavin <chris.lavin@xilinx.com> Signed-off-by: Jakob Wenzel <wenzel@rs.tu-darmstadt.de> * [PBlock] Add IsSoft and ExcludePlacement property in pblock (#1315) * [PBlock] Add IsSoft and ExcludePlacement property in pblock Signed-off-by: coherent17 <mnb51817@gmail.com> * [PBlock] Update getTclConstraints Signed-off-by: coherent17 <mnb51817@gmail.com> * [PBlock] reuse dcp in RapidWrightDCP to run test Signed-off-by: coherent17 <mnb51817@gmail.com> * [PblockProperty] Relocate PblockProperty and add unit test to test TclConstraints Signed-off-by: coherent17 <mnb51817@gmail.com> * [PblockProperty] Remove toString in PblockProperty Signed-off-by: coherent17 <mnb51817@gmail.com> --------- Signed-off-by: coherent17 <mnb51817@gmail.com> * apply more review suggestions Signed-off-by: Jakob Wenzel <wenzel@rs.tu-darmstadt.de> * link to class documentation for lookup Signed-off-by: Jakob Wenzel <wenzel@rs.tu-darmstadt.de> * add testcase Signed-off-by: Jakob Wenzel <wenzel@rs.tu-darmstadt.de> * Test constraints for parsing, stringifying and then parsing again Signed-off-by: Jakob Wenzel <wenzel@rs.tu-darmstadt.de> * add missing license header Signed-off-by: Jakob Wenzel <wenzel@rs.tu-darmstadt.de> * parse pblocks with XDCParser Signed-off-by: Jakob Wenzel <wenzel@rs.tu-darmstadt.de> * fix wrong import, fix license headers Signed-off-by: Jakob Wenzel <wenzel@rs.tu-darmstadt.de> * check XDCParser against all DCPs in RapidWrightDCP Signed-off-by: Jakob Wenzel <wenzel@rs.tu-darmstadt.de> * 2025.2.0-rc3, fixes #1320 Signed-off-by: Chris Lavin <chris.lavin@amd.com> * add roundtrip testing to TestConstraintTools Signed-off-by: Jakob Wenzel <wenzel@rs.tu-darmstadt.de> * test roundtrip for all xdc, speed up get_cells Signed-off-by: Jakob Wenzel <wenzel@rs.tu-darmstadt.de> * Updating reference to RapidWrightDCP Signed-off-by: Chris Lavin <chris.lavin@amd.com> --------- Signed-off-by: Jakob Wenzel <wenzel@rs.tu-darmstadt.de> Signed-off-by: Chris Lavin <chris.lavin@amd.com> Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> Signed-off-by: Andrew Butt <andrew.butt@amd.com> Signed-off-by: coherent17 <mnb51817@gmail.com> Co-authored-by: Chris Lavin <chris.lavin@amd.com> Co-authored-by: Andrew Butt <andrew.butt@amd.com> Co-authored-by: Chris Lavin <chris.lavin@xilinx.com> Co-authored-by: Coherent17 <mnb51817@gmail.com>

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

* Only remove top level Vivado bus prevention annotations Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Update src/com/xilinx/rapidwright/edif/EDIFCell.java Co-authored-by: Chris Lavin <chris.lavin@amd.com> Signed-off-by: Andrew Butt <andrew.butt@amd.com> * Update javadoc Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> --------- Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> Signed-off-by: Andrew Butt <andrew.butt@amd.com> Co-authored-by: Chris Lavin <chris.lavin@amd.com>

* [EDIFPort] Refactor getBitBlastedIndices() Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Check if isBus() Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Update src/com/xilinx/rapidwright/edif/EDIFPort.java Co-authored-by: eddieh-xlnx <eddie.hung@amd.com> Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fixing chronic misspelling of indices Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Update src/com/xilinx/rapidwright/edif/EDIFPort.java Co-authored-by: eddieh-xlnx <eddie.hung@amd.com> Signed-off-by: Chris Lavin <chris.lavin@amd.com> --------- Signed-off-by: Chris Lavin <chris.lavin@amd.com> Co-authored-by: eddieh-xlnx <eddie.hung@amd.com>

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

* Initial Schematic viewer with several issues. Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix minor issues Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fixes minor rendering issues Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fixes around labeling and refactoring Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix top port labels Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix hier-cell pin labels Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix hier button, still needs work for internal routes Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fixes nets inside expanded cells Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Move button to top left corner of expanded cells Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix padding/spacing around labels and buttons Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fixing multiple hier view, switch from EDIFCell->EDIFHierCellInst Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Basic selection using Strings, still WIP Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fixes various bugs Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Refactor to use all EDIFHier classes Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix disconnected ports Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix NPE Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix multi-level hierarchy issue. Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fixing Z layers Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Update for ELK and Guava license inclusion. Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Cleanup Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Temporarily remove cache Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Restore cache entry Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Update Jar test Signed-off-by: Chris Lavin <chris.lavin@amd.com> * List jars Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Rename cache Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Try new gradle home dir Signed-off-by: Chris Lavin <chris.lavin@amd.com> * More debug Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Remove env Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix NPE on inner port Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Enable top selection Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Add zoom to fit when selecting a new cell. Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Workaround to support JDK8 execution with ELK Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix selection of unexpanded tree items Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Simplify Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Attempt to allow selection from Python prompt Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Select from main thread Signed-off-by: Chris Lavin <chris.lavin@amd.com> * get startup sync correct Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fixing more issues, still WIP Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix missing top-level ports in the tree browser. Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix various NPEs, top port issues Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Cleanup after window closes Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Adds right-click copy menu on tree items Signed-off-by: Chris Lavin <chris.lavin@amd.com> --------- Signed-off-by: Chris Lavin <chris.lavin@amd.com>

* Updates for 2025.2.0 devices Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Update 2025.2.0 devices Signed-off-by: Chris Lavin <chris.lavin@amd.com> * rc4 Signed-off-by: Chris Lavin <chris.lavin@amd.com> * rc5 Signed-off-by: Chris Lavin <chris.lavin@amd.com> --------- Signed-off-by: Chris Lavin <chris.lavin@amd.com>

#1294) * Adds external library for netlists to compensate for black boxed cells Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Removing overconstrained check Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Add additional validity check in new EDIFPortInst() Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix failing test case after EDIFPortInst check Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Adds support for negative indexed busses on ports Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Adds example test of how to run Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Skip multiply_ip.dcp Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Test fix Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Updating RapidWrightDCP Signed-off-by: Chris Lavin <chris.lavin@amd.com> --------- Signed-off-by: Chris Lavin <chris.lavin@amd.com>

…#1326) Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

* Parallelize router initialization Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Start improving parallelism Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Parallelize createMissingSitePinInsts Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Clean up parallelization Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Switch to using futures to prevent accidentally hiding exceptions thrown in threads Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Fix NPE Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Fix concurrent modification issues Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Fix another concurrent modification issue Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Reduce synchronization and add caching on cells and pins Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Address comments Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add back sync Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Trying to fix failing test case Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Fix accidentally skipping some nets Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Cleanup Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add synchronization for rare case Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Remove fall-through if statements Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Fix additional early returns Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Use join instead of joinFirst Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * remove cell cache Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Remove re-lookup of cell Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Switch to integer map Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Fix bug from switching to integer site wires map Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Cleanup Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add back site wires copy Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add comment on synchronization Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * [DesignTools] Simplify Simplify createMissingSitePinInsts() Change getAllRoutedSitePinsFromPhysicalPin() Remove getSiteInstToNetSiteWiresMap() Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Cleanup Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Comments Signed-off-by: Eddie Hung <eddie.hung@amd.com> * createMissingSitePinInsts() to depend on makePhysNetNameConsistent() Thereby not needing to do parent net checks Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Cleanup Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Fix tests Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Undo accidental Signed-off-by: Eddie Hung <eddie.hung@amd.com> * [MergeDesigns] Clear logical net from physical net Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Double check before renaming Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Tidy Signed-off-by: Eddie Hung <eddie.hung@amd.com> * getSitePinInst() to be synchronized Signed-off-by: Eddie Hung <eddie.hung@amd.com> * CounterGenerator to flatten design Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Design.get{Gnd,Vcc}Net() outside of multi-threaded section Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Restore comment Signed-off-by: Eddie Hung <eddie.hung@amd.com> * No less than 100 objects per job Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Fix TestNet Signed-off-by: Eddie Hung <eddie.hung@amd.com> * [TestSiteInst] Add testAddPinDuplicate() Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Refactor Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Restore submodule Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Address review comments Signed-off-by: Eddie Hung <eddie.hung@amd.com> --------- Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> Signed-off-by: Eddie Hung <eddie.hung@amd.com> Signed-off-by: Chris Lavin <chris.lavin@amd.com> Co-authored-by: Andrew Butt <Andrew.Butt@amd.com> Co-authored-by: Chris Lavin <chris.lavin@amd.com>

* [VersalClockRouting] VDISTR tree storage map for Versal Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Preliminary v80 support Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Refactoring to use preferred clk root; adds VersalClockTree object Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Update storage format and file for vdistr paths on Versal Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Increasing the search space for clock root column candidates Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Apply suggestions from code review Signed-off-by: Chris Lavin <chris.lavin@amd.com> Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Add an assert Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Adds all Versal devices (except vp1902) Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Adding test to check that Versal distribution template in use Signed-off-by: Chris Lavin <chris.lavin@amd.com> * New data file fixes missing entries Signed-off-by: Chris Lavin <chris.lavin@amd.com> --------- Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

* [TestRWRoute] Initial testSLRCrossingNonTimingDriven for Versal Signed-off-by: Eddie Hung <eddie.hung@amd.com> * [RWRoute] Initial Versal SLR crossing support Signed-off-by: Eddie Hung <eddie.hung@amd.com> * More tests Signed-off-by: Eddie Hung <eddie.hung@amd.com> * [RouteNodeGraph] Dynamic SLL length Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Account for overshooting in Y due to SLLs Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Tidy Signed-off-by: Eddie Hung <eddie.hung@amd.com> * One more test Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Tidy Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Track NODE_SLL_DATA usage Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Fix end tile computation for SLL tiles Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Refactor routethru check Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Comments Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Only check NODE_CLE_BNODE for reaching SLRs Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Make INODEs for inter-SLR connections accessible Allowing INODE -> BOUNCE -> BNODE -> SLL_INPUT Signed-off-by: Eddie Hung <eddie.hung@amd.com> * RWRoute Versal SLR Crossing Test (#1327) * Bump RapidWrightDCP Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add Versal SLR crossing rwroute test Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> --------- Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Do not unroute since RWRoute unroutes anyway Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Incorporate fixed DCP Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix bad GUI constructor Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Fix PBlockRange XDC parser to handle multiple ranges in same cmd Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Updating submodule RapidWrightDCP Signed-off-by: Chris Lavin <chris.lavin@amd.com> * Tidy up Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Redundant Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Check grandparent instead of regex Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Update comment Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Test that no routethrus are used when terminating at LAG pin for FF Signed-off-by: Eddie Hung <eddie.hung@amd.com> * Apply suggestions from code review Signed-off-by: eddieh-xlnx <eddie.hung@amd.com> --------- Signed-off-by: Eddie Hung <eddie.hung@amd.com> Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> Signed-off-by: Chris Lavin <chris.lavin@amd.com> Signed-off-by: eddieh-xlnx <eddie.hung@amd.com> Co-authored-by: Andrew Butt <andrew.butt@amd.com> Co-authored-by: Chris Lavin <chris.lavin@amd.com>

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

* Add ability to constraint InlineFlops to a specific side of the PBlock to improve routability. Also unroute top-level I/O nets that exit the pblock. Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Use regex for port side map Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Address comments Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Update to new getBitBlastedIndices Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Remove unnecessary function calls Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add test case of unrouteTopLevelNetsThatLeavePBlock Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Remove extra imports Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add initial removeInlineFlops test Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Test remove inline flops and remove unnecessary code Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add back pin removal because of the specific case where a flop is in the same slice as a ground source Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Address comments and add new test cases Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Cleanup Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Update based on comment Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> --------- Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>

* Add ability to constraint InlineFlops to a specific side of the PBlock to improve routability. Also unroute top-level I/O nets that exit the pblock. Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Automate placement in ArrayBuilder Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Use regex for port side map Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Address comments Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Update to new getBitBlastedIndices Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Remove unnecessary function calls Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add test case of unrouteTopLevelNetsThatLeavePBlock Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Remove extra imports Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add initial removeInlineFlops test Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Test remove inline flops and remove unnecessary code Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add back pin removal because of the specific case where a flop is in the same slice as a ground source Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add ability to route array builder design Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Remove hardcoded placement constraints Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Handle null case Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Address comments and add new test cases Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Cleanup Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Address comments Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> --------- Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>

* Add ability to constraint InlineFlops to a specific side of the PBlock to improve routability. Also unroute top-level I/O nets that exit the pblock. Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Automate placement in ArrayBuilder Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Use regex for port side map Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Address comments Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Update to new getBitBlastedIndices Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Remove unnecessary function calls Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add test case of unrouteTopLevelNetsThatLeavePBlock Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Remove extra imports Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add initial removeInlineFlops test Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Test remove inline flops and remove unnecessary code Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add back pin removal because of the specific case where a flop is in the same slice as a ground source Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add ability to route array builder design Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Remove hardcoded placement constraints Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Handle null case Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Address comments and add new test cases Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Cleanup Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Start refactoring array builder Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Refactor mostly complete Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Time flop harness creation Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * More ArrayBuilder refactoring Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Move main Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Fix array builder failure Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Marge origin/array_builder_placement Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> * Add javadoc Signed-off-by: Andrew Butt <Andrew.Butt@amd.com> --------- Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

clavin-xlnx and others added 30 commits April 10, 2025 09:57

Merge master

f10322e

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

WIP - ArrayBuilder

8b55a0a

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Add missing header, import

b7bcbdd

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch 'master' into array_builder

7b5300f

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Adds a skip implementation option

e6695b6

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Avoids NPEs

8a42860

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch 'array_builder' of github.com:Xilinx/RapidWright into ar…

1fd15e4

…ray_builder Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Options for array construction

b311226

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch 'master' into array_builder

51fccb7

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Adding ArrayBuilder to main entrypoint

3feb912

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch 'master' into array_builder

f70c9eb

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge remote-tracking branch 'upstream/master' into array_builder

b9e7b1b

Copyright

ebf3721

Signed-off-by: Eddie Hung <eddie.hung@amd.com>

Add option to provide a top-level design

3d937a3

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch 'array_builder' of github.com:Xilinx/RapidWright into ar…

b6b8283

…ray_builder Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Work-around for blackbox handling

bc23ffe

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Update library when renaming cells; add API to remove bb prop

1730b70

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch 'master' into array_builder

7b52db2

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch 'edif_fixes' into array_builder

2487586

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Inline Flop Add/Removal Tool

d8c166c

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch 'master' into array_builder

0a76b2b

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

rc1

9dedc2a

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Adding a test

e15fe6d

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch 'inline_flop' into array_builder

ade5b5a

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch 'master' into array_builder

472b31c

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge encrypted cells from modules

521578f

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch '2025.1.2' into array_builder

c9eddb9

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch 'master' into array_builder

ea7b6d3

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch 'master' into array_builder

b0dc041

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

clavin-xlnx and others added 30 commits October 20, 2025 17:09

Merge branch 'master' into array_builder

c88b7ea

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Fix npe when no top dcp provided (#1301)

2caaf52

Signed-off-by: Andrew Butt <Andrew.Butt@amd.com>

Merge branch 'master' into 2025.2.0

67564c7

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch '2025.2.0' into array_builder

32d9138

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch 'master' into 2025.2.0

cfa360f

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Remove unnecessary methods, refactor name.

a4c2aba

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Refactor

0213db4

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch '2025.2.0' into array_builder

9115c67

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch '2025.2.0' into array_builder

1af0efc

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

[VersalClockRouting] Mark sink pins as routed once LCBs are connected (…

e2c7212

…#1326) Signed-off-by: Chris Lavin <chris.lavin@amd.com>

rc6

880346d

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

2025.2.0 jar

86afdcb

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch '2025.2.0' into array_builder

b60529c

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch 'master' into array_builder

a88f972

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

2025.2.1-rc1

1116dfb

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

Merge branch '2025.2.1' into array_builder

7fb223d

Signed-off-by: Chris Lavin <chris.lavin@amd.com>

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Array Builder Tool - Replicate Optimized Kernels in an Array #1163

Array Builder Tool - Replicate Optimized Kernels in an Array #1163

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clavin-xlnx commented Apr 10, 2025

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