This is a educational project for CPU_Design.

The project is still in a very initial stage, more information will be offered as soon as possible

Descriptions of each directory in the project:

rtl: The directory contains all the verilog sources for whu-riscv;

fpga: Stores FPGA-related files, such as constraint files or other information about boards;

tb: This directory contains the testbench files for simulation in EDA tools;

sim: This directory contains simulation batch files and scripts;

app: This directory contains not only the source code of the RV32 compliance test program, but also other applications, where the example directory has the source code of the C language program examples;

tools: This directory contains the GNU toolchain needed to compile assembly and C programs, the scripts required to convert binaries into mem format files for simulation, and the scripts for downloading programs through serial ports.

pics: Store pictures about the project;

doc: Store documents and important logs;

Copyright 2022-2022 School of Physics and Technology， Wuhan University