Label some SDK functions

headers/functions/arm9/libs.h

@@ -319,25 +319,73 @@ void EnableVramBanksInSet(struct vram_banks_set* vram_banks);
 void G3_LoadMtx43(struct matrix_4x3* matrix);
 void G3_MultMtx43(struct matrix_4x3* matrix);
 void GeomGxFifoSendMtx4x3(struct matrix_4x3* matrix, void* gxfifo);
+void OS_InitIrqTable(void);
+void OS_SetIrqFunction(uint32_t intr_bit, os_irq_function function);
+uint32_t OS_SetIrqMask(uint32_t mask);
+uint32_t OS_EnableIrqMask(uint32_t mask);
+uint32_t OS_DisableIrqMask(uint32_t mask);
+uint32_t OS_ResetRequestIrqMask(uint32_t mask);
+void OS_SetIrqStackChecker(void);
+void OS_InitLock(void);
+int OS_LockByWord(uint16_t lock_id, struct os_lock_word* lockp, lock_ctrl_funcp ctrl_funcp);
+int OSi_DoUnlockByWord(uint16_t lock_id, struct os_lock_word* lockp, lock_ctrl_funcp ctrl_funcp,
+                       bool disable_fiq);
+int OS_UnlockByWord(uint16_t lock_id, struct os_lock_word* lockp, lock_ctrl_funcp ctrl_funcp);
+int OS_UnlockCartridge(uint16_t lock_id);
+int OS_UnLockCartridge(uint16_t lock_id);
+void OSi_FreeCartridgeBus(void);
 int IncrementThreadCount(void);
+void OSi_InsertLinkToQueue(struct os_thread_queue* queue, struct thread* thread);
 void InsertThreadIntoList(struct thread* thread);
+void OS_RescheduleThread(void);
+void OS_InitThread(void);
 void StartThread(struct thread* thread, thread_entry_fn_t function, struct thread* param_3,
                  void* stack_area, int stack_size, int param_6);
 void ThreadExit(void);
+void OS_SleepThread(struct os_thread_queue* queue);
+void OS_WakeupThreadDirect(struct thread* thread);
+struct thread* OS_SelectThread(void);
+os_switch_thread_callback OS_SetSwitchThreadCallback(os_switch_thread_callback callback);
+void OSi_IdleThreadProc(void* arg);
 void SetThreadField0xB4(struct thread* thread, int value);
 void InitThread(struct thread* thread, void* function, void* stack_area_minus_4);
+bool OS_SaveContext(struct os_context* context);
+void OS_LoadContext(struct os_context* context);
+void OS_InitMutex(struct os_mutex* mutex);
+void DC_FlushAll(void);
+void DC_InvalidateRange(void* start_addr, uint32_t n_bytes);
+void DC_FlushRange(void* data, uint32_t size);
+void OSi_WaitVCount0(void);
+void OS_Init(void);
+void OS_InitArena(void);
+void OS_InitArenaEx(void);
+void* OS_GetInitArenaHi(enum os_arena_id id);
+void* OS_GetInitArenaLo(enum os_arena_id id);
+void OS_SetArenaHi(enum os_arena_id id, void* new_hi);
+void OS_SetArenaLo(enum os_arena_id id, void* new_lo);
+void OS_SetProtectionRegion1(uint32_t param);
+void OS_SetProtectionRegion2(uint32_t param);
+void OS_InitException(void);
+void OSi_ExceptionHandler(void);
 uint16_t GetTimer0Control(void);
+void OS_InitVAlarm(void);
 int ClearIrqFlag(void);
 int EnableIrqFlag(void);
 int SetIrqFlag(int new_value);
 int EnableIrqFiqFlags(void);
 int SetIrqFiqFlags(int new_value);
 int GetIrqFlag(void);
 int GetProcessorMode(void);
+void OS_InitReset(void);
 void GetDsFirmwareUserSettings(struct user_settings* settings);
 uint32_t CountLeadingZeros(uint32_t x);
+void OSi_InitVramExclusive(void);
 void WaitForever2(void);
 void WaitForInterrupt(void);
+void MI_SetWramBank(enum mi_wram cnt);
+void MI_DmaCopy16(uint32_t dma_no, void* src, void* dest, uint32_t size);
+void MI_StopDma(uint32_t dma_no);
+void MIi_CheckDma0SourceAddress(uint32_t dma_no, uint32_t src, uint32_t size, uint32_t dir);
 void ArrayFill16(uint16_t val, void* ptr, int len);
 void ArrayCopy16(void* src, void* dest, int len);
 void ArrayFill32(uint32_t val, void* ptr, int len);
@@ -347,14 +395,41 @@ void ArrayCopy32Fast(void* src, void* dest, int len);
 void MemsetFast(void* ptr, char val, uint32_t len);
 void MemcpyFast(void* src, void* dest, uint32_t n);
 uint32_t AtomicExchange(uint32_t desired, void* ptr);
+void MI_Init(void);
+void Pxi_Init(void);
+void Pxi_InitFifo(void);
+void Pxi_SetFifoRecvCallback(int fifo_tag, pxi_fifo_callback callback);
+void Pxi_IsCallbackReady(int fifo_tag, enum pxi_proc proc);
+int Pxi_SendWordByFifo(int fifo_tag, uint32_t data, bool err);
+void Pxii_HandlerRecvFifoNotEmpty(void);
 void FileInit(struct file_stream* file);
 bool GetOverlayInfo(struct overlay_info_entry* overlay_info, undefined param_2, int overlay_id);
 bool LoadOverlayInternal(struct overlay_info_entry* overlay_info);
 void InitOverlay(struct overlay_info_entry* overlay_info);
 void MD5_Init(undefined* ctx);
 void MD5_Update(undefined* ctx, const void* buf, size_t size);
 void MD5_Digest(uint32_t* hash, undefined* ctx);
+void PMi_CallCallbackAndUnlock(void);
+void PM_Init(void);
+void PMi_CommonCallback(void);
 uint32_t PM_ForceToPowerOff(void);
+void Cardi_InitCommon(void);
+void Card_Enable(bool enable);
+bool Cardi_ReadFromCache(struct card_rom_stat* p);
+void Cardi_SetRomOp(uint32_t cmd1, uint32_t cmd2);
+void Cardi_ReadCard(struct card_rom_stat* p);
+void Card_Init(void);
+struct card_rom_stat* Cardi_GetRomAccessor(void);
+void Cardi_OnFifoRecv(enum pxi_fifo_tag tag, uint32_t data, bool err);
+void Cardi_TaskThread(void* arg);
+void Card_InitPulledOutCallback(void);
+void Cardi_PulledOutCallback(enum pxi_fifo_tag tag, uint32_t data, bool err);
+void Ctrdgi_InitCommon(void);
+void Ctrdgi_ChangeLatestAccessCycle(struct ctrdg_rom_cycle* r);
+void Ctrdgi_RestoreAccessCycle(struct ctrdg_rom_cycle* r);
+void Ctrdgi_LockByProcessor(uint16_t lock_id, struct ctrdg_lock_by_proc* info);
+void Ctrdgi_UnlockByProcessor(uint16_t lock_id, struct ctrdg_lock_by_proc* info);
+void Ctrdgi_SendtoPxi(uint32_t data);
 
 // If declaring these builtins causes issues, you can disable them
 #ifndef PMDSKY_NO_BUILTIN

headers/types/common/enums.h

@@ -4287,4 +4287,63 @@ enum check_direction_option { CHECK_DIRECTION_NO = 0, CHECK_DIRECTION_YES = 1 };
 ENUM_8_BIT(box_type);
 #pragma pack(pop)
 
+enum os_thread_state {
+    OS_THREAD_STATE_WAITING = 0,
+    OS_THREAD_STATE_READY = 1,
+    OS_THREAD_STATE_TERMINATED = 2
+};
+
+enum os_arena_id {
+    OS_ARENA_MAIN = 0,
+    OS_ARENA_MAIN_SUBPRIV = 1,
+    OS_ARENA_MAINEX = 2,
+    OS_ARENA_ITCM = 3,
+    OS_ARENA_DTCM = 4,
+    OS_ARENA_SHARED = 5,
+    OS_ARENA_WRAM_MAIN = 6,
+    OS_ARENA_WRAM_SUB = 7,
+    OS_ARENA_WRAM_SUBPRIV = 8,
+    OS_ARENA_MAX = 9
+};
+
+enum mi_wram { MI_WRAM_ARM9_ALL = 0, MI_WRAM_1616_1 = 1, MI_WRAM_1616_2 = 2, MI_WRAM_ARM7_ALL = 3 };
+
+enum pxi_fifo_tag {
+    PXI_FIFO_TAG_EX = 0,     // Extension format
+    PXI_FIFO_TAG_USER_0,     // for application programmer, use it in free
+    PXI_FIFO_TAG_USER_1,     // for application programmer, use it in free
+    PXI_FIFO_TAG_SYSTEM,     // SDK inner usage
+    PXI_FIFO_TAG_NVRAM,      // NVRAM
+    PXI_FIFO_TAG_RTC,        // RTC
+    PXI_FIFO_TAG_TOUCHPANEL, // Touch Panel
+    PXI_FIFO_TAG_SOUND,      // Sound
+    PXI_FIFO_TAG_PM,         // Power Management
+    PXI_FIFO_TAG_MIC,        // Microphone
+    PXI_FIFO_TAG_WM,         // Wireless Manager
+    PXI_FIFO_TAG_FS,         // File System
+    PXI_FIFO_TAG_OS,         // OS
+    PXI_FIFO_TAG_CTRDG,      // Cartridge
+    PXI_FIFO_TAG_CARD,       // Card
+    PXI_FIFO_TAG_WVR,        // Control driving wireless library
+    PXI_FIFO_TAG_CTRDG_Ex,   // Cartridge Ex
+    PXI_MAX_FIFO_TAG = 32    // MAX FIFO TAG
+};
+
+enum pxi_proc { PXI_PROC_ARM9 = 0, PXI_PROC_ARM7 = 1 };
+
+enum mi_cartridge_rom_cycle_1st {
+    MI_CTRDG_ROMCYCLE1_10 = 0,
+    MI_CTRDG_ROMCYCLE1_8 = 1,
+    MI_CTRDG_ROMCYCLE1_6 = 2,
+    MI_CTRDG_ROMCYCLE1_18 = 3
+};
+
+enum mi_cartridge_rom_cycle_2nd { MI_CTRDG_ROMCYCLE2_6 = 0, MI_CTRDG_ROMCYCLE2_4 = 1 };
+
+enum os_intr_mode {
+    OS_INTRMODE_ENABLE = 0,
+    OS_INTRMODE_DISABLE_FIQ = 0x40,
+    OS_INTRMODE_DISABLE_IRQ = 0x80
+};
+
 #endif