Stabilize test/docs/gds

.gitignore

@@ -32,4 +32,6 @@ queue_test/tb.gtkw
 
 # testbench output related only
 sim.out
-output.log
+output.log
+docs/LOCAL_RUN.md
+scripts/run_tt_docker.sh

README.md

@@ -38,4 +38,4 @@ The GitHub action will automatically build the ASIC files using [OpenLane](https
 - Share your project on your social network of choice:
   - LinkedIn [#tinytapeout](https://www.linkedin.com/search/results/content/?keywords=%23tinytapeout) [@TinyTapeout](https://www.linkedin.com/company/100708654/)
   - Mastodon [#tinytapeout](https://chaos.social/tags/tinytapeout) [@matthewvenn](https://chaos.social/@matthewvenn)
-  - X (formerly Twitter) [#tinytapeout](https://twitter.com/hashtag/tinytapeout) [@tinytapeout](https://twitter.com/tinytapeout)
+  - X (formerly Twitter) [#tinytapeout](https://twitter.com/hashtag/tinytapeout) [@tinytapeout](https://twitter.com/tinytapeout)

docs/info.md

@@ -1,20 +1,18 @@
-<!---
-
-This file is used to generate your project datasheet. Please fill in the information below and delete any unused
-sections.
-
-You can also include images in this folder and reference them in the markdown. Each image must be less than
-512 kb in size, and the combined size of all images must be less than 1 MB.
--->
-
 ## How it works
 
-Explain how your project works
+This control module manages request and completion queues for SPI-based communication. It includes:
+- Request queue for incoming commands
+- Completion queue for completed operations
+- SPI for communication
+- AES and SHA FSM controllers for cryptographic operations
+- Bus arbiter for managing multi-source requests
 
 ## How to test
 
-Explain how to use your project
+- Run `make` in the test/ directory to execute all cocotb tests
+- Tests verify queue operations, SPI communication, and FSM functionality
+- Results are output to test/results.xml
 
 ## External hardware
 
-List external hardware used in your project (e.g. PMOD, LED display, etc), if any
+SPI Master/Host device for sending commands and receiving responses over MOSI/MISO lines

info.yaml

@@ -3,21 +3,29 @@ project:
   title:        "UWASIC-control-module"      # Project title
   author:       "UW-ASIC"      # Your name
   discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  ""      # One line description of what your project does
+  description:  "Control module for queue management and SPI communication"      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
-  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+  tiles: "2x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_example"
+  top_module:  "tt_um_control_top"
 
   # List your project's source files here.
   # Source files must be in ./src and you must list each source file separately, one per line.
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
-    - "control_top.v"
+    - "aes_fsm.v"
+    - "bus_arbiter.v"
+    - "comp_queue.v"
+    - "deserializer.v"
+    - "req_queue.v"
+    - "scoreboard.v"
+    - "serializer.v"
+    - "sha_fsm.v"
+    - "tt_um_control_top.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 # This section is for the datasheet/website. Use descriptive names (e.g., RX, TX, MOSI, SCL, SEG_A, etc.).

package.json

@@ -0,0 +1,10 @@
+{
+  "name": "control-group",
+  "version": "0.1.0",
+  "private": true,
+  "scripts": {
+    "lint:verilator": "verilator --lint-only --top-module tt_um_control_top src/*.v",
+    "lint:yosys": "yosys -p \"read_verilog src/*.v; hierarchy -check; proc; stat\"",
+    "lint": "npm run lint:verilator && npm run lint:yosys"
+  }
+}

src/aes_fsm.v

@@ -162,10 +162,10 @@ module aes_fsm #(
             end
             HASHOP: begin
                 arb_req = 1'b1;
-                data_out = {24'b0, r_req_data[73], 1'b0, ACCEL_ID, 4'b0011};
+                data_out = {24'b0, r_req_data[3*ADDRW+1], 1'b0, ACCEL_ID, 4'b0011};
             end
             WAIT_HASHOP: begin
-                data_out = {24'b0, r_req_data[73], 1'b0, ACCEL_ID, 4'b0011};
+                data_out = {24'b0, r_req_data[3*ADDRW+1], 1'b0, ACCEL_ID, 4'b0011};
             end
             MEMWR: begin
                 arb_req = 1'b1;

src/comp_queue.v

@@ -18,18 +18,33 @@ module comp_queue #(
 );
 
     // VCD dump for simulation
+`ifndef SYNTHESIS
     initial begin
         $dumpfile("tb.vcd");
         $dumpvars(0, comp_queue);
     end
+`endif
 
     // Internal FIFO
     reg [ADDRW-1:0] mem [0:QDEPTH-1];
-    reg [$clog2(QDEPTH)-1:0] head, tail;
-    reg [$clog2(QDEPTH+1)-1:0] count;
+    // Calculate index and count widths based on QDEPTH 
+    // Handles edge cases like QDEPTH <= 1, force min width to be 1
+    localparam integer IDXW = (QDEPTH <= 1) ? 1 : $clog2(QDEPTH);
+    localparam integer COUNTW = (QDEPTH <= 1) ? 1 : $clog2(QDEPTH + 1);
+    function [IDXW-1:0] idx_const;
+        input integer value;
+        begin
+            idx_const = value[IDXW-1:0];
+        end
+    endfunction
+    localparam [IDXW-1:0] LAST_IDX = idx_const(QDEPTH - 1);
+    localparam [COUNTW-1:0] COUNT_MAX = QDEPTH;
+
+    reg [IDXW-1:0] head, tail;
+    reg [COUNTW-1:0] count;
 
-    wire full  = (count == QDEPTH);
-    wire empty = (count == 0);
+    wire full  = (count == COUNT_MAX);
+    wire empty = (count == {COUNTW{1'b0}}); // zero width
 
     // Round-robin selector: 0 = AES, 1 = SHA
     reg rr_select;
@@ -53,27 +68,30 @@ module comp_queue #(
     end
 
     wire deq_valid = !empty;
-    wire deq_ready = ready_in && valid_out;
 
     always @(posedge clk or negedge rst_n) begin
         if (!rst_n) begin
-            head <= 0;
-            tail <= 0;
-            count <= 0;
+            head <= {IDXW{1'b0}};
+            tail <= {IDXW{1'b0}};
+            count <= {COUNTW{1'b0}};
             rr_select <= 0;
             valid_out <= 0;
             data_out <= 0;
         end else begin
-            // Debug output around failing cycle
+            // Debug output around failing cycle (simulation only)
+`ifndef SYNTHESIS
             if ($time >= 2250000 && $time <= 2290000) begin
                 $display("[%0t] rr_select=%0b | valid_in_aes=%b valid_in_sha=%b | aes_sel=%b sha_sel=%b | enq_valid=%b enq_ready=%b | count=%0d | tail=%0d",
                     $time, rr_select, valid_in_aes, valid_in_sha, aes_sel, sha_sel, enq_valid, enq_ready, count, tail);
             end
+`endif
 
             // Enqueue logic
             if (enq_valid && enq_ready) begin
                 mem[tail] <= enq_data;
-                tail <= (tail + 1) % QDEPTH;
+                // avoid modulo on mixed widths to prevent WIDTHTRUNC warnings
+                if (tail == LAST_IDX) tail <= {IDXW{1'b0}};
+                else tail <= tail + 1;
                 count <= count + 1;
             end
 
@@ -84,7 +102,10 @@ module comp_queue #(
             // Dequeue logic
             if (deq_valid && ready_in) begin
                 data_out <= mem[head];
-                head <= (head + 1) % QDEPTH;
+                if (head == LAST_IDX)       // (head + 1) % QDEPTH
+                    head <= {IDXW{1'b0}};
+                else 
+                    head <= head + 1;
                 count <= count - 1;
             end
 
@@ -93,4 +114,4 @@ module comp_queue #(
         end
     end
 
-endmodule
+endmodule

src/deserializer.v

@@ -4,15 +4,15 @@ module deserializer #(
     parameter ADDRW   = 24,
     parameter OPCODEW = 2
 ) (
-    //INPUTS: clk, rst_n, spi_clk, mosi, cs_n, aes_ready_in, sha_ready_in
+    // INPUTS: clk, rst_n, spi_clk, mosi, cs_n, aes_ready_in, sha_ready_in
     input  wire               clk,
     input  wire               rst_n,
     input  wire               spi_clk,
     input  wire               mosi,
     input  wire               cs_n,
     input  wire               aes_ready_in,
     input  wire               sha_ready_in,
-    //OUTPUTS: opcode[1:0], key_addr[ADDRW-1:0], text_addr[ADDRW-1:0], valid_out
+    // OUTPUTS: opcode[1:0], key_addr[ADDRW-1:0], text_addr[ADDRW-1:0], valid_out
     output reg                valid, 
     output reg  [OPCODEW-1:0] opcode,     
     output reg  [ADDRW-1:0]   key_addr,
@@ -21,9 +21,10 @@ module deserializer #(
     output reg                valid_out
 );
 
+    // clog2 helper function for calculating bit widths
     function integer clog2;
         input integer value;
-        integer v, n;  // <-- declare n
+        integer v, n;       // delacre n
         begin
             if (value <= 1) begin
                 clog2 = 1;
@@ -38,18 +39,22 @@ module deserializer #(
             end
         end
     endfunction
-    localparam integer SHIFT_W = 1 + OPCODEW + (3 * ADDRW); 
-    localparam integer CW = clog2(SHIFT_W + 1);  
 
-    //Synchronize
+    // Total instruction width: [valid(1b), opcode(OPCODEW), key_addr, text_addr, dest_addr]
+    localparam integer SHIFT_W = 1 + OPCODEW + (3 * ADDRW);
+    // Bits needed to count from 0 to SHIFT_W-1
+    localparam integer CW = clog2(SHIFT_W + 1);
+    localparam [CW-1:0] CNT_FULL = SHIFT_W - 1;
+
+    // synchronize
     reg [1:0] r_clk;
     reg [1:0] r_cs_n;
     reg [1:0] r_mosi;    
 
     always @(posedge clk or negedge rst_n) begin
         if (!rst_n) begin       // Changed to active-low reset
             r_clk <= 2'b00;     // Changed from 3'b00
-            r_cs_n <= 2'b11;
+            r_cs_n <= 2'b11;    // Inactive
             r_mosi <= 2'b00;
         end else begin
             r_clk <= {r_clk[0], spi_clk};
@@ -58,10 +63,8 @@ module deserializer #(
         end
     end
 
-    //Shift Data
+    // shift data
     wire clk_posedge = (r_clk == 2'b01);  // detected posedge of spi_clk (0->1)
-    wire cs_active  = ~r_cs_n[1];   // active-low CS
-    wire mosi_s = r_mosi[1];
 
     reg [CW-1:0] cnt;  // how many bits of current word have been collected
     reg [SHIFT_W-1:0] shift_reg;
@@ -76,7 +79,7 @@ module deserializer #(
             opcode     <= {OPCODEW{1'b0}};
             key_addr   <= {ADDRW{1'b0}};
             text_addr  <= {ADDRW{1'b0}};
-            dest_addr  <= {ADDRW{1'B0}}; 
+            dest_addr  <= {ADDRW{1'b0}}; 
             valid_out  <= 1'b0;
         end else begin
             valid_out <= 1'b0;  // one-cycle pulse default
@@ -86,7 +89,7 @@ module deserializer #(
                 if (clk_posedge && !busy) begin
                     // shift in data
                     shift_reg <= {shift_reg[SHIFT_W-2:0], r_mosi[1]};
-                    if (cnt == (SHIFT_W-1)) begin
+                    if (cnt == CNT_FULL) begin
                         busy <= 1'b1;                 // full word captured
                         cnt  <= {CW{1'b0}};
                     end else begin
@@ -128,4 +131,4 @@ module deserializer #(
 
         end
     end
-endmodule
+endmodule