Pinned Loading

1. FPGA_Accelerator FPGA_Accelerator Public

   Hardware accelerator for ray marching (a rendering technique), synthesised on an SoC FPGA.

   VHDL 1

2. RISCV-Group23 RISCV-Group23 Public

   Forked from luqeei1/RISCV-Group23

   Design and simulation of a pipelined RISC-V CPU, with caching and branch prediction. Compatible with the RV32I instruction set.

   C++

3. C90_To_RISCV_Compiler C90_To_RISCV_Compiler Public

   Lexer, Parser, and Code Generator for C90, with target language being RISCV.

   C++

4. Various_Projects Various_Projects Public

   Collection of RTL hardware projects: 1) Parallel, pipelined, bitonic sort module

   SystemVerilog

5. FPGA_Game FPGA_Game Public

   Forked from lucasvenetz/InfoProc23

   Sword Fighting game

   Verilog

6. Optimised-Decision-Tree Optimised-Decision-Tree Public

   A decision tree constructor and destructor, optimised with the fewest tree nodes possible using information gain and entropy analysis of input data.

   C++