Skip to content

Commit e76d721

Browse files
committed
all timer tests pass
1 parent e594cdf commit e76d721

File tree

1 file changed

+6
-3
lines changed

1 file changed

+6
-3
lines changed

src/test/scala/tech/rocksavage/chiselware/timer/TimerBasicTests.scala

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -219,7 +219,9 @@ object TimerBasicTests extends AnyFlatSpec with ChiselScalatestTester {
219219
val prescalerAddr = registerMap.getAddressOfRegister("prescaler").get
220220
val maxCountAddr = registerMap.getAddressOfRegister("maxCount").get
221221

222-
val rand = new scala.util.Random
222+
val rand = new scala.util.Random
223+
val unix_ms = System.currentTimeMillis()
224+
rand.setSeed(unix_ms)
223225
val maxCountValue = rand.nextInt(50) + 1 // Ensure non-zero
224226
val prescalerValue = rand.nextInt(5)
225227

@@ -231,8 +233,9 @@ object TimerBasicTests extends AnyFlatSpec with ChiselScalatestTester {
231233
writeAPB(dut.io.apb, enAddr.U, 1.U)
232234

233235
// Calculate expected total cycles
234-
val expectedTotalCycles = maxCountValue * (prescalerValue + 1)
235-
var cycles = 0
236+
val expectedTotalCycles =
237+
maxCountValue * (prescalerValue + 1) - 1 // -1 for apb write
238+
var cycles = 0
236239

237240
while (
238241
!dut.io.timerOutput.maxReached

0 commit comments

Comments
 (0)