maxcount interrupt

Author: nickrallison

src/main/scala/tech/rocksavage/chiselware/timer/Timer.scala

@@ -22,7 +22,6 @@ class Timer(val timerParams: TimerParams, formal: Boolean) extends Module {
     val io = IO(new Bundle {
         val apb         = new ApbBundle(ApbParams(dataWidth, addressWidth))
         val timerOutput = new TimerOutputBundle(timerParams)
-        val interrupt   = new TimerInterruptBundle
     })
 
     // Create a RegisterMap to manage the addressable registers
@@ -47,6 +46,9 @@ class Timer(val timerParams: TimerParams, formal: Boolean) extends Module {
     val setCount: Bool = RegInit(false.B)
     registerMap.createAddressableRegister(setCount, "setCount", verbose = timerParams.verbose)
 
+    val maxCountEnableInterrupt: Bool = RegInit(false.B)
+    registerMap.createAddressableRegister(maxCountEnableInterrupt, "maxCountEnableInterrupt", verbose = timerParams.verbose)
+
     // println("Register Map: " + registerMap.getRegisters)
 
     // Generate AddrDecode
@@ -86,11 +88,8 @@ class Timer(val timerParams: TimerParams, formal: Boolean) extends Module {
     timerInner.io.timerInputBundle.maxCount      := maxCount
     timerInner.io.timerInputBundle.pwmCeiling    := pwmCeiling
     timerInner.io.timerInputBundle.setCountValue := setCountValue
+    timerInner.io.timerInputBundle.maxCountEnableInterrupt := maxCountEnableInterrupt
     // Connect the TimerInner outputs to the top-level outputs
     io.timerOutput <> timerInner.io.timerOutputBundle
-    // Handle interrupts
-    io.interrupt.interrupt := TimerInterruptEnum.None
-    when(timerInner.io.timerOutputBundle.maxReached) {
-        io.interrupt.interrupt := TimerInterruptEnum.MaxReached
-    }
+
 }

src/main/scala/tech/rocksavage/chiselware/timer/TimerInner.scala

@@ -43,6 +43,8 @@ class TimerInner(
     val pwmCeilingWire    = WireInit(0.U(params.countWidth.W))
     val setCountValueWire = WireInit(0.U(params.countWidth.W))
     val setCountWire      = WireInit(false.B)
+    val maxCountEnableInterruptWire = WireInit(false.B)
+
 
     // Assign input signals to wires
     enWire            := io.timerInputBundle.en
@@ -51,6 +53,7 @@ class TimerInner(
     pwmCeilingWire    := io.timerInputBundle.pwmCeiling
     setCountValueWire := io.timerInputBundle.setCountValue
     setCountWire      := io.timerInputBundle.setCount
+    maxCountEnableInterruptWire := io.timerInputBundle.maxCountEnableInterrupt
 
     // ###################
     // Output
@@ -60,21 +63,25 @@ class TimerInner(
     val countNext      = WireInit(0.U(params.countWidth.W))
     val maxReachedNext = WireInit(false.B)
     val pwmNext        = WireInit(false.B)
+    val maxCountInterruptNext = WireInit(false.B)
 
     // Registers for output signals
     val countReg      = RegInit(0.U(params.countWidth.W))
     val maxReachedReg = RegInit(false.B)
     val pwmReg        = RegInit(false.B)
+    val maxCountInterruptReg = RegInit(false.B)
 
     // Assign next values to registers
     countReg      := countNext
     maxReachedReg := maxReachedNext
     pwmReg        := pwmNext
+    maxCountInterruptReg := maxCountInterruptNext
 
     // Assign registers to output bundle
     io.timerOutputBundle.count      := countReg
     io.timerOutputBundle.maxReached := maxReachedReg
     io.timerOutputBundle.pwm        := pwmReg
+    io.timerOutputBundle.interrupts.maxCountInterrupt := maxCountInterruptReg
 
     // ###################
     // Internal
@@ -137,6 +144,13 @@ class TimerInner(
       prescaler = prescalerWire
     )
 
+    // Interrupts
+    maxCountInterruptNext := false.B
+    when(maxReachedNext && maxCountEnableInterruptWire) {
+        maxCountInterruptNext := true.B
+    }
+
+
     // ###################
     // Formal verification
     // ###################
@@ -195,6 +209,13 @@ class TimerInner(
             when(prescalerStableLow3 && setCountStableLow3) {
                 assert(prescalerCounterNext <= prescalerWire)
             }
+
+            // ######################
+            // Interrupt Specification
+            // ######################
+            when (maxReachedFV && maxCountEnableInterruptWire) {
+                assert(maxCountInterruptNext)
+            }
         }
     }
 

src/main/scala/tech/rocksavage/chiselware/timer/bundle/TimerInputBundle.scala

@@ -32,4 +32,7 @@ class TimerInputBundle(params: TimerParams) extends Bundle {
     /** Signal to set the counter to `setCountValue`. */
     val setCount = Input(Bool())
 
+    /** Signal to enable the interrupt when the counter reaches the maximum count. */
+    val maxCountEnableInterrupt = Input(Bool())
+
 }

src/main/scala/tech/rocksavage/chiselware/timer/bundle/TimerInterruptBundle.scala

@@ -6,5 +6,5 @@ import chisel3._
 import chisel3.util._
 
 class TimerInterruptBundle extends Bundle {
-    val interrupt = Output(TimerInterruptEnum())
+    val maxCountInterrupt = Output(Bool())
 }

src/main/scala/tech/rocksavage/chiselware/timer/bundle/TimerOutputBundle.scala

@@ -22,4 +22,7 @@ class TimerOutputBundle(params: TimerParams) extends Bundle {
 
     /** PWM output signal with a duty cycle controlled by `pwmCeiling`. */
     val pwm = Output(Bool())
+
+    /** Interrupt signals for the timer. */
+    val interrupts = new TimerInterruptBundle
 }

src/test/scala/tech/rocksavage/chiselware/timer/TimerInnerFVHarness.scala

@@ -42,6 +42,7 @@ class TimerInnerFVHarness(
     val pwmCeilingReg    = RegInit(0.U(params.countWidth.W))
     val setCountValueReg = RegInit(0.U(params.countWidth.W))
     val setCountReg      = RegInit(false.B)
+    val maxCountEnableInterruptReg = RegInit(false.B)
 
     // Assignment
     enReg            := io.timerInputBundle.en
@@ -50,6 +51,7 @@ class TimerInnerFVHarness(
     pwmCeilingReg    := io.timerInputBundle.pwmCeiling
     setCountValueReg := io.timerInputBundle.setCountValue
     setCountReg      := io.timerInputBundle.setCount
+    maxCountEnableInterruptReg := io.timerInputBundle.maxCountEnableInterrupt
 
     // ###################
     // Output
@@ -59,6 +61,7 @@ class TimerInnerFVHarness(
     val countNext      = WireInit(0.U(params.countWidth.W))
     val maxReachedNext = WireInit(false.B)
     val pwmNext        = WireInit(false.B)
+    val maxCountInterruptNext = WireInit(false.B)
 
     // ###################
     // Module Instantiation
@@ -72,12 +75,15 @@ class TimerInnerFVHarness(
     timerInner.io.timerInputBundle.pwmCeiling    := pwmCeilingReg
     timerInner.io.timerInputBundle.setCountValue := setCountValueReg
     timerInner.io.timerInputBundle.setCount      := setCountReg
+    timerInner.io.timerInputBundle.maxCountEnableInterrupt := maxCountEnableInterruptReg
 
     countNext      := timerInner.io.timerOutputBundle.count
     maxReachedNext := timerInner.io.timerOutputBundle.maxReached
     pwmNext        := timerInner.io.timerOutputBundle.pwm
+    maxCountInterruptNext := timerInner.io.timerOutputBundle.interrupts.maxCountInterrupt
 
     io.timerOutputBundle.count      := countNext
     io.timerOutputBundle.maxReached := maxReachedNext
     io.timerOutputBundle.pwm        := pwmNext
+    io.timerOutputBundle.interrupts.maxCountInterrupt := maxCountInterruptNext
 }