Welcome to my journey through the SoC Tapeout Program VSD!
This repository documents my week-by-week progress with tasks inside each week.
"In this program, we learn to design a System-on-Chip (SoC) from basic RTL to GDSII using open-source tools. Part of India’s largest collaborative RISC-V tapeout initiative, empowering 3500+ participants to build silicon and advance the nation’s semiconductor ecosystem
| Task | Description | Status |
|---|---|---|
| [Task 0] | 🛠️ [Tools Installation] — Installed Iverilog, Yosys, and gtkWave | ✅ Done |
- Installed and verified open-source EDA tools successfully.
- Learned about basic environment setup for RTL design and synthesis.
- Prepared the system for upcoming RTL → GDSII flow experiments.
I am thankful to Kunal Ghosh and Team VLSI System Design (VSD) for the opportunity to participate in the ongoing RISC-V SoC Tapeout Program.
I also acknowledge the support of RISC-V International, India Semiconductor Mission (ISM), VLSI Society of India (VSI), and Efabless for making this initiative possible.
🔗 Program Links:
