GitHub - TERMIN20/PongFPGA: Pong Game For DE1-SoC VGA Display in System Verilog

TERMIN20 / PongFPGA Public

Pong Game For DE1-SoC VGA Display in System Verilog

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Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
CLOCK25_PLL		CLOCK25_PLL
CLOCK25_PLL_sim		CLOCK25_PLL_sim
db		db
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
work		work
.gitattributes		.gitattributes
CLOCK25_PLL.bsf		CLOCK25_PLL.bsf
CLOCK25_PLL.cmp		CLOCK25_PLL.cmp
CLOCK25_PLL.ppf		CLOCK25_PLL.ppf
CLOCK25_PLL.qip		CLOCK25_PLL.qip
CLOCK25_PLL.sip		CLOCK25_PLL.sip
CLOCK25_PLL.spd		CLOCK25_PLL.spd
CLOCK25_PLL.v		CLOCK25_PLL.v
CLOCK25_PLL_sim.f		CLOCK25_PLL_sim.f
DE1_SoC.qpf		DE1_SoC.qpf
DE1_SoC.qsf		DE1_SoC.qsf
DE1_SoC.srf		DE1_SoC.srf
DE1_SoC.sv		DE1_SoC.sv
DE1_SoC.sv.bak		DE1_SoC.sv.bak
DE1_SoC_golden_top.sdc		DE1_SoC_golden_top.sdc
DE1_SoC_nativelink_simulation.rpt		DE1_SoC_nativelink_simulation.rpt
Launch_ModelSim.bat		Launch_ModelSim.bat
ProgramTheDE1_SoC.cdf		ProgramTheDE1_SoC.cdf
altera_up_avalon_video_vga_timing.v		altera_up_avalon_video_vga_timing.v
c5_pin_model_dump.txt		c5_pin_model_dump.txt
clock_divider.sv		clock_divider.sv
pong_game.sv		pong_game.sv
pong_game.sv.bak		pong_game.sv.bak
pong_renderer.sv		pong_renderer.sv
pong_renderer.sv.bak		pong_renderer.sv.bak
runlab.do		runlab.do
transcript		transcript
video_driver.sv		video_driver.sv
vsim.wlf		vsim.wlf
wave.do		wave.do