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Sarunesh/README.md

Hi there 👋, Myself SARUNESH S

RTL Design and Verification engineer from India!

LinkedIn Instagram

Hardware Description and Verification languages

Verilog SystemVerilog

Verification methodology

UVM

Tools/Platforms

Questasim Modelsim EDAplayground Quartus Prime Lite gVim

Other Languages and Tools:

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  1. VLSI VLSI Public

    This repos contains the links for all of my VLSI repositories

    2