Universal Verification Methodology of a simple Memory

This project describes the design of a simple memory and also the verification of this design with the help of the UVM.

Instructions

This repository contains two SystemVerilog scripts, one for the design of the memory and one for the verification of this design. Also contain a .txt file in witch you cand see the functionability of this project on EDa Playground.

Installing

This project can be viewed online in the EDA Playground by clicking on this link.