PEEK: Heterogeneous Parallelism for Privileged Error Detection in Safety-Critical Processors

This repository contains artefacts and workflows (Parsec 3.0) to reproduce experiments for "PEEK: Heterogeneous Parallelism for Privileged Error Detection in Safety-Critical Processors"

Platform pre-requisities

• An x86-64 system (more cores will improve simulation time).
• Linux operating system (we used Ubuntu 20.04 and Ubuntu 22.04)
• An AMD U280 FPGA (for FPGA simulation)

Dependencies Installation

Step 1. Building simulation platform, RISC-V toolchain, Chisel toolchain, and other dependencies:

git clone https://github.com/ucb-bar/chipyard.git
cd chipyard
git checkout 1.13.1
./scripts/init-submodules-no-riscv-tools.sh
./scripts/build-toolchains.sh riscv-tools # for a normal risc-v toolchain 

Hardware

Step 1. Setting environments:

export PEEK=$(dirname $(pwd))
export PLATFORM=$(pwd)
. ./env.sh

Step 2. Updating the source code, ensuring to achieve the latest version:

$PEEK/Scripts/update_src.sh

Step 3. Building hardware for PEEK:

cd $PLATFORM/sims/verilator
make config=PEEKProConfig

(OUTPUT I) After a few hours, a software simulator and the corresponding Verilog code will be generated:

./simulator-chipyard-PEEKProConfig # Software Simulator
./generated-src/chipyard.TestHarness.PEEKProConfig/chipyard.TestHarness.PEEKProConfig.top.v # Verilog code

Software

To run Parsec, both Linux kernel and Parsec are required to be compiled:

Step 1. For Linux, downloading the kernel code:

git clone https://github.com/firesim/linux
git checkout firesim-v57

(OUTPUT II) With that, compiling the kernel using following steps: link

Step 2. For Parsec, compiling checker thread first:

cd $PEEK/Software/checker_thread
make checker_thread

After the compilation, a checker_thread.o is generated.

Step 3. Now, compiling Parsec and link the checker_thread.o:

cd $PEEK/Software/parsec/pkgs
./build_parsec.sh

(OUTPUT III ) After a few minutes, the Parsec is compiled with the checker_thread.o:

./app # Parsec benchmark
./run_parsec.sh # Scripts to run all Parsec benchmark

FPGA Simulation

With the above steps, hardware and software are generated.

Deploying the hardware on the U280 FPGA using standard Xilinx steps or FireSim: link

The Verilog is generated in (OUTPUT I), and the OS kernel and workload are in (OUTPUT II & III).

(The SPEC06 is reproduced in the same way.)