Name		Name	Last commit message	Last commit date
Latest commit History 25 Commits
ipynb		ipynb
scripts		scripts
src		src
.gitattributes		.gitattributes
.gitignore		.gitignore
Makefile		Makefile
README.md		README.md
Veryl.lock		Veryl.lock
Veryl.toml		Veryl.toml

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pynq_uart

PL 側から UART 出したい

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fpga uart pynq ultra96-v2 veryl

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