Design and Analyses of CMOS-Inverter.

NOV-2024 ---- DEC-2024.

This work focuses on designing, simulating, and analyzing NMOS, PMOS, and CMOS inverter circuits using Cadence Virtuoso with the GPDK90 technology library. The goal of the project was to understand how basic CMOS devices behave under different operating conditions and how their characteristics affect overall circuit performance.

The process began with creating schematics for NMOS and PMOS transistors with proper biasing. DC analysis was performed to study I–V characteristics, transconductance, and power consumption. The results clearly show how current changes with gate and drain voltages, matching typical MOSFET behavior. Parametric analysis was also carried out by varying temperature and body bias, and it was observed that NMOS and PMOS currents decrease with higher temperature, while threshold voltage shifts with body biasing.

Next, a CMOS inverter was designed using matched NMOS and PMOS devices. The inverter’s Voltage Transfer Characteristic (VTC) was plotted, and sizing adjustments were made to achieve VM ≈ VDD/2. Current and power behavior of the inverter were analyzed, showing peak current around the switching threshold. Transient analysis with a pulse input confirmed proper inversion with expected rise and fall times.

Further studies included parametric width variation, temperature effects, and body-bias impact on the inverter’s switching point. A Monte Carlo analysis was performed to understand statistical variations due to manufacturing differences.

Finally, the layout of the CMOS inverter was drawn, followed by DRC and LVS checks to ensure the layout matched the schematic. Ring padding was added to meet layout design rules.

Overall, this project provides complete hands-on experience in CMOS device modeling, analysis, inverter design, and physical layout verification, helping build a strong foundation in analog VLSI design.