backport subject "iommu/riscv: Add irqbypass support" #149

yechao-w · 2025-10-13T03:10:15Z

反合iommu irqbypass相关补丁。具体的验证方法见issue单：
#148

mainline inclusion from mainline-v6.12-rc1 commit 01415e7 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Replace the dummy implementation for PCI related functions with actual implementation. This needs ECAM and MCFG CONFIG options to be enabled for RISC-V. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-10-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> [Resolve merge conflicts in arch/riscv/Kconfig] Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.12-rc1 commit f8bba14 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- On RISC-V platforms, the RINTC structures should be probed before any other interrupt controller structures and IMSIC before APLIC. This order is established by using MADT sub table types which are ordered in the incremental order from the RINTC. So, add the architecture function for RISC-V to reorder the interrupt controller probing as per the hierarchy like below. ACPI_MADT_TYPE_RINTC = 24, ACPI_MADT_TYPE_IMSIC = 25, ACPI_MADT_TYPE_APLIC = 26, ACPI_MADT_TYPE_PLIC = 27 This means processing all RINTC structures (in the order of appearance in MADT), followed by IMSIC strucutre and then all APLIC/PLIC structures. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-11-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> [Resolve merge conflicts in drivers/acpi/riscv/Makefile] Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.12-rc1 commit e77b8dc category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- RISC-V has PLIC and APLIC in MADT as well as namespace devices. Initialize the list of those structures using MADT and namespace devices to create mapping between the ACPI handle and the GSI ranges. This will be used later to add dependencies. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-12-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.12-rc1 commit 1b173cc category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- RISC-V interrupt controllers for wired interrupts are platform devices and hence their driver will be probed late. Also, APLIC which is one such interrupt controller can not be probed early since it needs MSI services. This needs a probing order between the interrupt controller driver and the device drivers. _DEP is typically used to indicate such dependencies. However, the dependency may be already available like GSI mapping. Hence, instead of an explicit _DEP, architecture can find the implicit dependencies and add to the dependency list. For RISC-V, add the dependencies for below use cases. 1) For devices which has IRQ resource, find out the interrupt controller using GSI number map and add the dependency. 2) For PCI host bridges: a) If _PRT indicate PCI link devices, add dependency on the link device. b) If _PRT indicates GSI, find out the interrupt controller using GSI number map and add the dependency. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-13-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.12-rc1 commit f8619b6 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- The RINTC subtype structure in MADT also has information about other interrupt controllers. Save this information and provide interfaces to retrieve them when required by corresponding drivers. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Björn Töpel <bjorn@rivosinc.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20240812005929.113499-14-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.12-rc1 commit aa143df category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- While populating IMSIC global structure, many fields are initialized using DT properties. Make the code which uses DT properties as separate function so that it is easier to add ACPI support later. No functionality added/changed. Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Björn Töpel <bjorn@rivosinc.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20240812005929.113499-15-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.12-rc1 commit fbe826b category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- RISC-V IMSIC interrupt controller provides IPI and MSI support. Currently, DT based drivers setup the IPI feature early during boot but defer setting up the MSI functionality. However, in ACPI systems, PCI subsystem is probed early and assume MSI controller is already setup. Hence, both IPI and MSI features need to be initialized early itself. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Björn Töpel <bjorn@rivosinc.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20240812005929.113499-16-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.12-rc1 commit 5122e38 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Add ACPI support in APLIC drivers. Use the mapping created early during boot to get the details about the APLIC. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Björn Töpel <bjorn@rivosinc.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20240812005929.113499-17-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> [Resolve merge conflicts in drivers/irqchip/irq-riscv-aplic-msi.c] Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.12-rc1 commit 206dd13 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Add ACPI support in PLIC driver. Use the mapping created early during boot to get details about the PLIC. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Co-developed-by: Haibo Xu <haibo1.xu@intel.com> Signed-off-by: Haibo Xu <haibo1.xu@intel.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Björn Töpel <bjorn@rivosinc.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20240812005929.113499-18-sunilvl@ventanamicro.com [ rjw: Rebase on top of recent irqchip changes ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.12-rc4 commit a98a0f0 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- When CONFIG_SMP is disabled, the static array rintc_acpi_data with size NR_CPUS is not sufficient to hold all RINTC structures passed from the firmware. All RINTC structures are required to configure IMSIC/APLIC/PLIC properly irrespective of SMP in the OS. So, allocate dynamic memory based on the number of RINTC structures in MADT to fix this issue. Fixes: f8619b6 ("irqchip/riscv-intc: Add ACPI support for AIA") Reported-by: Björn Töpel <bjorn@kernel.org> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/all/20241014065739.656959-1-sunilvl@ventanamicro.com Closes: https://github.com/linux-riscv/linux-riscv/actions/runs/11280997511/job/31375229012 Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.10-rc1 commit d7f546c category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/50 -------------------------------- The timer capability to wakeup the cpu irrespective of its idle state is provided by the flag in RHCT. Update the timer code to set this flag. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20230927170015.295232-5-sunilvl@ventanamicro.com Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.10-rc1 commit e8065df category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/50 -------------------------------- Enhance the acpi_os_ioremap() to support opregions in MMIO space. Also, have strict checks using EFI memory map to allow remapping the RAM similar to arm64. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231018124007.1306159-2-sunilvl@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.10-rc1 commit a068352 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/50 -------------------------------- acpi_get_rhct() currently returns pointer to acpi_table_header structure. But since this is specific to RHCT, return pointer to acpi_table_rhct structure itself. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20231018124007.1306159-3-sunilvl@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.10-rc1 commit 9ca8756 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/50 -------------------------------- Cache Block Operation (CBO) related block size in ACPI is provided by RHCT. Add support to read the CMO node in RHCT to get this information. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20231018124007.1306159-4-sunilvl@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.10-rc1 commit 2960f37 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/50 -------------------------------- Initialize the CBO variables on ACPI based systems using information in RHCT. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20231018124007.1306159-5-sunilvl@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

community inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/52 Reference: https://gitee.com/bianbu-linux/linux-6.6/commit/c28bef14d50d830b0c16b986cfd9ba04bd83f5fd -------------------------------- Add memory range interconnect process for k1, because of the address space is inconsistent among various devices. cpu address space is: 0x0_0000_0000~0x0_7fff_ffff: dram area (low 2GB dram) 0x0_8000_0000~0x0_ffff_ffff: device register area 0x1_0000_0000~0x4_7fff_ffff: dram area (high 14GB dram ) address for dma/usb/sdmmc for ex. is: 0x0_0000_0000~0x0_7fff_ffff: dram area (low 2GB dram) only 2GB dram area can be accessed address space for vpu/gpu/dpu/v2d/isp/csi for ex. is: 0x0_0000_0000~0x0_ffff_ffff: dram area (low 4GB dram) only 4GB area can be accessed address space for dma/pcie0/pcie1/pcie2 for ex. is: 0x0_0000_0000~0x0_7fff_ffff: dram area (low 2GB dram) 0x0_8000_0000~0x0_ffff_ffff: device register area 0x1_0000_0000~0x4_7fff_ffff: dram area (high 14GB dram) Signed-off-by: zhangmeng <zhangmeng.kevin@linux.spacemit.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

community inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/52 Reference: https://gitee.com/bianbu-linux/linux-6.6/commit/cd1ec77f104056aa1b50f562f9683c4365696e07 -------------------------------- There are 3 types of memory range for devices: 1. 1st type is 2GB access only 2. 2nd type is 4GB access only 3. 3rd type is 14GB access support. Signed-off-by: zhangmeng <zhangmeng.kevin@linux.spacemit.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

community inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/52 Reference: https://gitee.com/bianbu-linux/linux-6.6/commit/cd1ec77f104056aa1b50f562f9683c4365696e07 -------------------------------- Signed-off-by: zhangmeng <zhangmeng.kevin@linux.spacemit.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.10-rc5 commit d6ecd18 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/57 -------------------------------- Enable the dmi driver for riscv which would allow access the SMBIOS info through some userspace file(/sys/firmware/dmi/*). The change was based on that of arm64 and has been verified by dmidecode tool. Signed-off-by: Haibo Xu <haibo1.xu@intel.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20240613065507.287577-1-haibo1.xu@intel.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

community inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/47 -------------------------------- Add ACPI ID SOPH0002 to support SG2044 UART controller. Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

community inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/47 -------------------------------- SG2044 Implemented MSI interrupt controller to support PCIe devices to request MSI interrupts, add driver to support it. Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

community inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/47 -------------------------------- Add SOPH0003 to the ACPI APD support list to ensure correct clock settings for the I2C devices on the Sophgo SG2044 platforms. Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

community inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/47 -------------------------------- Add SOPH0004 to the ACPI APD support list to ensure correct clock settings for the SPI devices on the Sophgo SG2044 platforms. Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.13-rc1 commit 4877fc9 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/67 -------------------------------- Enable Low Power Idle (LPI) based cpuidle driver for RISC-V platforms. It depends on SBI HSM calls for idle state transitions. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://lore.kernel.org/r/20240118062930.245937-3-sunilvl@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.13-rc1 commit 359df7c category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/67 -------------------------------- The ACPI processor driver is not currently enabled for RISC-V. This is required to enable CPU related functionalities like LPI and CPPC. Hence, enable ACPI_PROCESSOR for RISC-V. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://lore.kernel.org/r/20240118062930.245937-4-sunilvl@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.9-rc1 commit 9ca5fac category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/48 -------------------------------- Add str_plural() helper to replace existing open implementations used by many drivers and help improve future user facing messages. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://lore.kernel.org/r/20240214165015.1656-1-michal.wajdeczko@intel.com Signed-off-by: Kees Cook <keescook@chromium.org> [Resolve merge conflicts in include/linux/string_choices.h] Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.13-rc1 commit 2631c2b category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/48 -------------------------------- Sophgo SG2044 has a new version of T-HEAD C920, which implement a fully featured T-HEAD ACLINT device. This ACLINT device contains a SSWI device to support fast S-mode IPI. Add necessary compatible string for the T-HEAD ACLINT SSWI device. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/all/20241031060859.722258-2-inochiama@gmail.com Link: https://www.xrvm.com/product/xuantie/C920 Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.13-rc1 commit 25caea9 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/48 -------------------------------- Add a driver for the T-HEAD C900 ACLINT SSWI device. This device allows the system with T-HEAD cpus to send ipi via fast device interface. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20241031060859.722258-3-inochiama@gmail.com [Resolve merge conflicts in drivers/irqchip/Kconfig] [Resolve merge conflicts in drivers/irqchip/Makefile] [Resolve compilation error in drivers/irqchip/irq-thead-c900-aclint-sswi.c] [Resolve merge conflicts in include/linux/cpuhotplug.h] Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

community inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/48 -------------------------------- Add ACPI support in ACLINT-SSWI early probe. Treat ACLINT-SSWI as a fake IMSIC that can only handle IPIs in a software manner. Use the IMSIC-related fields in the MADT table to obtain the register base address of ACLINT-SSWI. Signed-off-by: Jingyu Li <jingyu.li01@sophgo.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

mainline inclusion from mainline-v6.11-rc2 commit f15c21a category: feature bugzilla: RVCK-Project#63 -------------------------------- Add arch_trigger_cpumask_backtrace() which is a generic infrastructure for sampling other CPUs' backtrace using IPI. The feature is used when lockups are detected or in case of oops/panic if parameters are set accordingly. Below is the case of oops with the oops_all_cpu_backtrace enabled. $ sysctl kernel.oops_all_cpu_backtrace=1 triggering oops shows: [ 212.214237] NMI backtrace for cpu 1 [ 212.214390] CPU: 1 PID: 610 Comm: in:imklog Tainted: G OE 6.10.0-rc6 RVCK-Project#1 [ 212.214570] Hardware name: riscv-virtio,qemu (DT) [ 212.214690] epc : fallback_scalar_usercopy+0x8/0xdc [ 212.214809] ra : _copy_to_user+0x20/0x40 [ 212.214913] epc : ffffffff80c3a930 ra : ffffffff8059ba7e sp : ff20000000eabb50 [ 212.215061] gp : ffffffff82066f90 tp : ff6000008e958000 t0 : 3463303866660000 [ 212.215210] t1 : 000000000000005b t2 : 3463303866666666 s0 : ff20000000eabb60 [ 212.215358] s1 : 0000000000000386 a0 : 00007ff6e81df926 a1 : ff600000824df800 [ 212.215505] a2 : 000000000000003f a3 : 7fffffffffffffc0 a4 : 0000000000000000 [ 212.215651] a5 : 000000000000003f a6 : 0000000000000000 a7 : 0000000000000000 [ 212.215857] s2 : ff600000824df800 s3 : ffffffff82066cc0 s4 : 0000000000001c1a [ 212.216074] s5 : ffffffff8206a5a8 s6 : 00007ff6e81df926 s7 : ffffffff8206a5a0 [ 212.216278] s8 : ff600000824df800 s9 : ffffffff81e25de0 s10: 000000000000003f [ 212.216471] s11: ffffffff8206a59d t3 : ff600000824df812 t4 : ff600000824df812 [ 212.216651] t5 : ff600000824df818 t6 : 0000000000040000 [ 212.216796] status: 0000000000040120 badaddr: 0000000000000000 cause: 8000000000000001 [ 212.217035] [<ffffffff80c3a930>] fallback_scalar_usercopy+0x8/0xdc [ 212.217207] [<ffffffff80095f56>] syslog_print+0x1f4/0x2b2 [ 212.217362] [<ffffffff80096e5c>] do_syslog.part.0+0x94/0x2d8 [ 212.217502] [<ffffffff800979e8>] do_syslog+0x66/0x88 [ 212.217636] [<ffffffff803a5dda>] kmsg_read+0x44/0x5c [ 212.217764] [<ffffffff80392dbe>] proc_reg_read+0x7a/0xa8 [ 212.217952] [<ffffffff802ff726>] vfs_read+0xb0/0x24e [ 212.218090] [<ffffffff803001ba>] ksys_read+0x64/0xe4 [ 212.218264] [<ffffffff8030025a>] __riscv_sys_read+0x20/0x2c [ 212.218453] [<ffffffff80c4af9a>] do_trap_ecall_u+0x60/0x1d4 [ 212.218664] [<ffffffff80c56998>] ret_from_exception+0x0/0x64 Signed-off-by: Ryo Takakura <takakura@valinux.co.jp> Link: https://lore.kernel.org/r/20240718093659.158912-1-takakura@valinux.co.jp Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> [Since Euler has modified the return type of arch_trigger_cpumask_backtrace in a previous commit, we also need to make the same change. Refer to “nmi: backtrace: Allow runtime arch specific override”.] Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit e719d000b44f498552dc054c044fbb85d47a0340 category: feature bugzilla: RVCK-Project#148 -------------------------------- Provide a domain bus token for the upcoming support for the RISC-V IOMMU interrupt remapping domain, which needs to be distinguished from NEXUS domains. The new token name is generic, as the only information that needs to be conveyed is that the IRQ domain will remap MSIs, i.e. there's nothing RISC-V specific to convey. Since the MSI_REMAP domain implements init_dev_msi_info() with msi_parent_init_dev_msi_info(), which makes 'domain' point to the NEXUS domain, while keeping 'msi_parent_domain' pointing to itself, there's nothing to do in msi-lib to add support except to accept the token. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit 9a75e28174789adab08b9c513f5dcf11ac364c23 category: feature bugzilla: RVCK-Project#148 -------------------------------- In order to add the interrupt remapping support in a separate file, share struct riscv_iommu_domain and struct riscv_iommu_info through the header. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit 994cbb6b4108bcde54ec180d5a8f5c4fdfb72ffa category: feature bugzilla: RVCK-Project#148 -------------------------------- The parameter will be increased when we need to set up more fields in the device context. Use a data structure to wrap them up. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit 730685282f8369002101a97c697d8dd0c160c1ba category: feature bugzilla: RVCK-Project#148 -------------------------------- This is just a skeleton. Until irq-set-affinity functions are implemented the IRQ domain doesn't serve any purpose. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit e3a7d1b1afcef4a0b4248b9eb54d89c3daaba1cd category: feature bugzilla: RVCK-Project#148 -------------------------------- Capture the IMSIC layout from its config and reserve all the addresses. Then use the IMSIC layout info to calculate the maximum number of PTEs the MSI table needs to support and allocate the MSI table when attaching a paging domain for the first time. Finally, at the same time, map the IMSIC addresses in the stage1 DMA table when the stage1 DMA table is not BARE. This ensures it doesn't fault as it will translate the addresses before the MSI table does. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit ccb3320533baed34cd0ee8187ea56026beff5d3e category: feature bugzilla: RVCK-Project#148 -------------------------------- Export more in iommu.h from iommu.c and implement functions needed to manage the MSI table. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit 49c19bda42a6c54c37a96fbbc76b0ef7632a5aca category: feature bugzilla: RVCK-Project#148 -------------------------------- The riscv iommu uses a specific set of bits for PPNs (53:10). Export the translation functions so iommu-ir can use them as well. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit f3f5933a70d4e7134592bf53370f18a70097c07a category: feature bugzilla: RVCK-Project#148 -------------------------------- When setting irq affinity extract the IMSIC address the device needs to access and add it to the MSI table. If the device no longer needs access to an IMSIC then remove it from the table to prohibit access. This allows isolating device MSIs to a set of harts so we can now add the IRQ_DOMAIN_FLAG_ISOLATED_MSI IRQ domain flag. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

category: feature bugzilla: RVCK-Project#148 -------------------------------- Refer to other archs to add the implementation of the probe_finalize interface, and install dma_ops for device in this interface. So the IOMMU_DMA can be enabled on riscv. Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit 2fa0f64858256011e7fcdbeae774644038f4041d category: feature bugzilla: RVCK-Project#148 -------------------------------- With iommu/riscv driver available we can enable IOMMU_DMA support for RISC-V architecture. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit b5bb8d1e192fdfae1744585cffb613d3e339cdc9 category: feature bugzilla: RVCK-Project#148 -------------------------------- The vcpu_info parameter to irq_set_vcpu_affinity() effectively defines an arch specific IOMMU <=> hypervisor protocol. Provide a definition for the RISCV IOMMU. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit 6eccd59c7c162c734d1763c1b7bce2888bee6338 category: feature bugzilla: RVCK-Project#148 -------------------------------- Track each IRQ's MSI table index in the IRQ's chip data of the IR irqdomain along with a generation number. This will be necessary when support for irq-set-vcpu-affinity is added as the msitbl configuration will change to match the guest. When a configuration changes then it may no longer be possible to compute the index from the target address, hence the need to stash it. Also, if an allocated IRQ is not mapped with irq-set-vcpu-affinity after a configuration change (which will unmap everything), then we need to avoid attempting to unmap it at free-irqs time. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit e8257d34f5cf0038a63cb2cea23d8417adcfd1cf category: feature bugzilla: RVCK-Project#148 -------------------------------- Implement irq_set_vcpu_affinity() in the RISCV IOMMU driver. irq_set_vcpu_affinity() is the channel from a hypervisor to the IOMMU needed to ensure that assigned devices which direct MSIs to guest IMSIC addresses will have those MSI writes redirected to their corresponding guest interrupt files. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit 027a636133cb54386e60e9a0dfad29fcbf70cf74 category: feature bugzilla: RVCK-Project#148 -------------------------------- Report RISC-V IOMMU capability required by the VFIO subsystem to enable PCIe device assignment. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit 01149585d0247d7077b43857fbe492d09978904b category: feature bugzilla: RVCK-Project#148 -------------------------------- Enable KVM/VFIO support on RISC-V architecture. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

mainline inclusion from mainline-v6.16-rc3 commit cb21073 category: feature bugzilla: RVCK-Project#148 -------------------------------- When updating IRTEs in response to a GSI routing or IRQ bypass change, pass the new/current routing information along with the associated irqfd. This will allow KVM x86 to harden, simplify, and deduplicate its code. Since adding/removing a bypass producer is now conveniently protected with irqfds.lock, i.e. can't run concurrently with kvm_irq_routing_update(), use the routing information cached in the irqfd instead of looking up the information in the current GSI routing tables. Opportunistically convert an existing printk() to pr_info() and put its string onto a single line (old code that strictly adhered to 80 chars). ------ Adjust for rvck-6.6, just change the kvm_arch_update_irqfd_routing params. No function changed. Link: https://lore.kernel.org/r/20250611224604.313496-5-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

mainline inclusion from mainline-v6.16-rc3 commit b33252b category: feature bugzilla: RVCK-Project#148 -------------------------------- Don't bother WARNing if updating an IRTE route fails now that vendor code provides much more precise WARNs. The generic WARN doesn't provide enough information to actually debug the problem, and has obviously done nothing to surface the myriad bugs in KVM x86's implementation. Drop all of the associated return code plumbing that existed just so that common KVM could WARN. Link: https://lore.kernel.org/r/20250611224604.313496-34-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit fbd94a31b5faaf653386213a0e2b2e8a31df6e54 category: feature bugzilla: RVCK-Project#148 -------------------------------- Add all the functions needed to wire up irqbypass support and implement kvm_arch_update_irqfd_routing() which makes irq_set_vcpu_affinity() calls whenever the assigned device updates its target addresses. Also implement calls to irq_set_vcpu_affinity() from kvm_riscv_vcpu_aia_imsic_update() which are needed to update the IOMMU mappings when the hypervisor migrates a VCPU to another CPU (requiring a change to the target guest interrupt file). Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit 65d9439d4cb593478f640aa2e75ca3f4c4288d16 category: feature bugzilla: RVCK-Project#148 -------------------------------- Enable VFIO support on RISC-V architecture. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

from https://github.com/jones-drew/linux/commits/riscv/iommu-irqbypass-rfc-v2/ commit 1635f7df4b480273bf1cf7604af6a5e07675f6c7 category: feature bugzilla: RVCK-Project#148 -------------------------------- Add the VFIO modules to the defconfig to complement KVM now that there is IOMMU support. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>

github-actions · 2025-10-13T03:10:33Z

开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/18453966153

参数解析结果

args	value
repository	RVCK-Project/rvck
head ref	pull/149/head
base ref	rvck-6.6
LAVA repo	RVCK-Project/lavaci
LAVA Template	lava-job-template/qemu/qemu-ltp.yaml
Testcase path	lava-testcases/common-test/ltp/ltp.yaml

测试完成

详细结果:

RVCK result

check	result
kunit-test	success
kernel-build	failure
lava-trigger	skipped
check-patch	success

Kunit Test Result

[03:16:34] Testing complete. Ran 455 tests: passed: 443, skipped: 12

Kernel Build Result

Kernel build failed.

Check Patch Result


Total Errors	9
Total Warnings	47

yechao-w · 2025-10-13T12:41:41Z

/check

开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/18466133272

参数解析结果

args	value
repository	RVCK-Project/rvck
head ref	pull/149/head
base ref	rvck-6.6
LAVA repo	RVCK-Project/lavaci
LAVA Template	lava-job-template/qemu/qemu-ltp.yaml
Testcase path	lava-testcases/common-test/ltp/ltp.yaml

测试完成

详细结果:

RVCK result

check	result
kunit-test	success
kernel-build	failure
lava-trigger	skipped
check-patch	success

Kunit Test Result

[12:49:01] Testing complete. Ran 455 tests: passed: 443, skipped: 12

Kernel Build Result

Kernel build failed.

Check Patch Result


Total Errors	9
Total Warnings	47

sterling-teng · 2026-01-22T16:06:45Z

ping

sterling-teng · 2026-02-01T09:34:58Z

该pr长期未活动，还有更新计划吗？

yechao-w · 2026-02-02T01:08:52Z

上游社区最新的补丁还没有出来，后续会跟进。看是先关闭这个PR，后面再重新用新的PR合入？ @sterling-teng

sterling-teng · 2026-02-02T14:00:24Z

上游社区最新的补丁还没有出来，后续会跟进。看是先关闭这个PR，后面再重新用新的PR合入？ @sterling-teng

保留你的推送分支，先关闭该pr，后面可以重新打开该pr。

vlsunil and others added 30 commits October 8, 2025 14:21

yechao-w and others added 20 commits October 13, 2025 10:58

sterling-teng force-pushed the rvck-6.6 branch from f29e160 to 4783446 Compare November 3, 2025 00:08

sterling-teng force-pushed the rvck-6.6 branch from 163fdec to 39d59e7 Compare November 30, 2025 17:56

sterling-teng force-pushed the rvck-6.6 branch from ee07355 to a3af7f5 Compare December 31, 2025 00:27

sterling-teng force-pushed the rvck-6.6 branch from 6e7299d to 3fb06be Compare February 1, 2026 18:16

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backport subject "iommu/riscv: Add irqbypass support" #149

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