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LVS passes for cells at the block level but shows errors for the same cells at the top level

Status: Open.

#103 In RTimothyEdwards/netgen;

· d-m-bailey opened on Dec 3, 2025

netgen infinite loop

Status: Open.

#101 In RTimothyEdwards/netgen;

· d-m-bailey opened on Nov 20, 2025

CDL model names of the format $[model_name] do not match model_name

Status: Open.

#100 In RTimothyEdwards/netgen;

· d-m-bailey opened on Nov 13, 2025

Calling an verilog module from spice no longer works.

Status: Open.

#94 In RTimothyEdwards/netgen;

· d-m-bailey opened on Aug 22, 2024

Possible problem with mixed device types.

Status: Open.

#93 In RTimothyEdwards/netgen;

· d-m-bailey opened on Aug 14, 2024

Possible problem with verilog port processing

Status: Open.

#92 In RTimothyEdwards/netgen;

· d-m-bailey opened on Aug 8, 2024

' might be causing problems when used as part of a net name

Status: Open.

#91 In RTimothyEdwards/netgen;

· d-m-bailey opened on Jun 18, 2024

netcmp.c / MatchPins

Status: Open.

#88 In RTimothyEdwards/netgen;

· ymei opened on May 9, 2024

Multiple ports connected with verilog assign do not match.

Status: Open.

#87 In RTimothyEdwards/netgen;

· d-m-bailey opened on Feb 9, 2024

'M' Property Error on Single PNP

Status: Open.

#86 In RTimothyEdwards/netgen;

· d-m-bailey opened on Jan 4, 2024

make install fails [tclnetgen.dylib] Error 1

Status: Open.

#85 In RTimothyEdwards/netgen;

· bertgoz opened on Dec 3, 2023

Using netgen to generate ".sim" files from ".spice" netlists

Status: Open.

#84 In RTimothyEdwards/netgen;

· mhajimorad opened on Oct 26, 2023