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added CI to README 01_warm-up #54: Commit a756d88 pushed by tojauch
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added CI to README 02_ALU #3: Commit a756d88 pushed by tojauch
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Add CI badge for ALU pipeline in README 02_ALU #2: Commit 4db9cdd pushed by tojauch
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Add CI badge for ALU pipeline in README 01_warm-up #53: Commit 4db9cdd pushed by tojauch
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added task 02 02_ALU #1: Commit 1f2a979 pushed by tojauch
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added task 02 01_warm-up #52: Commit 1f2a979 pushed by tojauch
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WS2526: Warm-Up Task 01_warm-up #48: Commit 47dd8a2 pushed by tojauch
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initial commit for WS2526 02_single-cycle_RISC-V_core #47: Commit 55edeb9 pushed by tojauch
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initial commit for WS2526 04_pipelined_RISC-V_core #41: Commit 55edeb9 pushed by tojauch
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initial commit for WS2526 01_warm-up #47: Commit 55edeb9 pushed by tojauch
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initial commit for WS2526 05_pipelined_RISC-V_core_hazardDetection #27: Commit 55edeb9 pushed by tojauch
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initial commit for WS2526 03_multi-cycle_RISC-V_core #43: Commit 55edeb9 pushed by tojauch
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added project task description 02_single-cycle_RISC-V_core #46: Commit 8e5e15b pushed by tojauch
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added project task description 04_pipelined_RISC-V_core #40: Commit 8e5e15b pushed by tojauch
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added project task description 03_multi-cycle_RISC-V_core #42: Commit 8e5e15b pushed by tojauch
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added project task description 05_pipelined_RISC-V_core_hazardDetection #26: Commit 8e5e15b pushed by tojauch
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added project task description 01_warm-up #46: Commit 8e5e15b pushed by tojauch
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fixed CI pipeline (SBT not available on latest Ubuntu) 01_warm-up #32: Commit fbb8813 pushed by tojauch
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fixed CI pipeline (SBT not available on latest Ubuntu) 03_multi-cycle_RISC-V_core #28: Commit fbb8813 pushed by tojauch
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fixed CI pipeline (SBT not available on latest Ubuntu) 04_pipelined_RISC-V_core #26: Commit fbb8813 pushed by tojauch
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fixed CI pipeline (SBT not available on latest Ubuntu) 02_single-cycle_RISC-V_core #32: Commit fbb8813 pushed by tojauch
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fixed CI pipeline (SBT not available on latest Ubuntu) 05_pipelined_RISC-V_core_hazardDetection #12: Commit fbb8813 pushed by tojauch
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added explanations on implicit clock and reset to Chisel introduction 03_multi-cycle_RISC-V_core #24: Commit b716d54 pushed by tojauch
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added explanations on implicit clock and reset to Chisel introduction 04_pipelined_RISC-V_core #22: Commit b716d54 pushed by tojauch
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added explanations on implicit clock and reset to Chisel introduction 05_pipelined_RISC-V_core_hazardDetection #8: Commit b716d54 pushed by tojauch
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