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The output channel also needs a pipelined endian swap path. |
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This makes several improvements to the SPI Bus. The result is that SCK frequency may now be 1/4 the base clock rather than 1/8. This is accomplished by removing the cycle delay in multi-byte word handling through pipelining. There are also some improvements to the idioms used. We do not need to explicitly tribuf the SPI SCK/CS lines and synchronize. We use the implicit Verilog idioms for this, which makes it a little bit easier to read. Utilization and clock frequency is around the same +/- 0.5% or so.