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dont brake motor on disable #113

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2 changes: 1 addition & 1 deletion sim_microstepper.ys
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,6 @@ read_verilog -sv testbench/microstepper_tb.v \
src/microstepper/mytimer_8.v \
src/microstepper/mytimer_10.v

prep -top testbench
prep -top microstepper_tb
show microstepper_top
sim -n 400000 -clock clk -vcd testbench/microstepper.vcd
4 changes: 2 additions & 2 deletions src/microstepper/microstepper_control.v
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Expand Up @@ -80,9 +80,9 @@ module microstepper_control (
// Low side output polarity, enable, and fault shutdown
// Outputs are active high unless config_invert_**** is set
assign phase_a1_l_out = config_invert_lowside ^ ( phase_a1_l | !enable );
assign phase_a2_l_out = config_invert_lowside ^ ( phase_a2_l | !enable );
assign phase_a2_l_out = config_invert_lowside ^ ( phase_a2_l && faultn && enable );
assign phase_b1_l_out = config_invert_lowside ^ ( phase_b1_l | !enable );
assign phase_b2_l_out = config_invert_lowside ^ ( phase_b2_l | !enable );
assign phase_b2_l_out = config_invert_lowside ^ ( phase_b2_l && faultn && enable );

// High side
assign phase_a1_h_out = config_invert_highside ^ ( phase_a1_h && faultn && enable );
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