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APx Gen2 Phase2 RCT

Checkout existing RCT code and APx Core Firmware connector from:

git clone --recursive ssh://git@gitlab.cern.ch:7999/asvetek/phase2-rct.git -b 384b
git clone git@github.com:SridharaDasu/CMSPhase2RCT.git
cd CMSPhase2RCT
git checkout RCT-Gen2-384-Bit 
source setEnv.sh #(uwlogin/beck independent)

Simulation

For HLS simulation:

cd $AP_FW_BASE_DIR/CMSPhase2RCT/hls/vivado_hls/
vivado_hls -f run_hls.tcl csim=1 tv_in=$PWD/data/test_in.txt tv_out=$PWD/data/test_out.txt tv_ref=$PWD/data/test_out_ref.txt

Sythesis

For HLS synthesis and exporting RTl:

cd $AP_FW_BASE_DIR/CMSPhase2RCT/hls/vivado_hls/
vivado_hls -f run_hls.tcl synth=1 export=1 

The whole enchilada

Simulation, Synthesis, Verification and RTL generation in Vivado HLS (takes 2 hours):

cd $AP_FW_BASE_DIR/CMSPhase2RCT/hls/vivado_hls/
vivado_hls -f run_hls.tcl csim=1 synth=1 cosim=1 export=1 tv_in=$PWD/data/test_in.txt tv_out=$PWD/data/test_out.txt tv_ref=$PWD/data/test_out_ref.txt

The nightcap

Making the bit file for APd (takes hours):

cd $AP_FW_BASE_DIR/phase2-rct/
mkdir build
make

GUI access

Follow instructions at twiki - adapt suitably for usage on beck.hep.wisc.edu: https://twiki.cern.ch/twiki/bin/viewauth/CMS/L1TriggerPhase2HLSProjects

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CMS Phase2 RCT HLS Project

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  • VHDL 48.1%
  • C++ 25.1%
  • SystemVerilog 16.3%
  • Python 3.7%
  • Tcl 3.4%
  • Makefile 2.3%
  • Other 1.1%