Work in Progress
Verilog Ethernet stack by Alex Forencich
Hardware Assisted IEEE1588. Includes RTC and TSU.
- Implementation of PTPv2 slave in E2E configuration;
- Synchronization accuracy up to 7 μs; (work in progress)
- Calculation of offset and rtt;
- Direct time adjustment;
- Precise time adjustment with PI-regulator; (work in progress)
- No BMC algorithm. (not planned)
This project was created as part of bachelors thesis for St. Petersburg Polytechnic Univercity. When testing on board, it was connected to White Rabbit Switch, which regularly sends PTP packets. Announce messages are ignored.
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