feat(rvt): support Risc-V tensor instruction test#64
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sploving1 wants to merge 1 commit intoOpenXiangShan:masterfrom
Open
feat(rvt): support Risc-V tensor instruction test#64sploving1 wants to merge 1 commit intoOpenXiangShan:masterfrom
sploving1 wants to merge 1 commit intoOpenXiangShan:masterfrom
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This commit adds a comprehensive test application to validate the RISC-V tensor (RVT) extension implementation in NEMU.
Key additions:
New test application at apps/rvt-trigger/trigger.c that thoroughly exercises the RVT instruction set
Dual implementation approach providing both CPU reference and tensor accelerator execution paths
End-to-end validation of the complete tensor workflow including configuration, data transfer, and computation
Test Application Features:
Reference CPU implementation (matmul_cpu) - Standard triple-loop matrix multiplication for baseline comparison
Tensor accelerator workflow demonstrating:
TCSR (Tensor Control and Status Registers) configuration for matrices A, B, and C
Synchronized data transfers between system memory and URAM
Execution of tensor matrix multiplication instructions using inline assembly
Verification mechanism comparing accelerator results against CPU reference with detailed error reporting
Configurable test dimensions (M=16, K=32, N=64) suitable for simulation environments