feat(difftest): decouple clockgate from fpga_sim

[klin02]

To prepare for upcoming pipeline refactoring, this change decouples clockgate
and ref_clock from fpga_sim. In addition to FPGA AXI, clockgate can now also be
reused by the Delta, enabling Difftest to process data from a single DUT cycle
across multiple cycles.

[poemonsense]

Please let @xiaokamikami have a review. I may not have enough time to review the details in the future

Suggestion:

Since now we are defining the SimTop in Chisel, some logic in top.v should be moved into Chisel under SimTop, especially the module connections. For example, the clock and clock gate can be moved into Chisel.

[poemonsense]

For verilog modules whose design do not depend on run-time arguments, they should be put in src directory.

[klin02]

We originally put clockgate under generate to simplify include-path management across different build configs. It is used not only by FPGA/FPGA_SIM but also when Delta is enabled, so it may be hard to give it an appropriate path under src.

In addition, files under src need to be explicitly copied into fpga-release, it may be simplified when put it in generate.

[klin02]

Please let @xiaokamikami have a review. I may not have enough time to review the details in the future

Suggestion:

Since now we are defining the SimTop in Chisel, some logic in top.v should be moved into Chisel under SimTop, especially the module connections. For example, the clock and clock gate can be moved into Chisel.

On FPGA, core_clock is shared by the DUT(SimTop), memories, and peripherals. And the enable condition may also consider some xdma-related signals, which are not accessible inside SimTop.
Therefore we place the clockgate outside the SimTop so that it can both observe the required XDMA signals and correctly gate the global core_clock domain for all modules.

[klin02]

In this PR, since pipeline-based backpressure had not yet been introduced,
Gateway was still required to run on the gated core_clock rather than ref_clock.
However, due to an error in the fpga_sim scripts at that time, the CI tests in
this PR did not catch this failure.

The pipeline-based refactoring in PR #802 corrected the clocking to match the
intended behavior, and PR #805 fixed the fpga_sim CI tests to properly detect
such issues.