fix(SimJTAG): remove wire delays for newer version of verilator

[cyyself]

In newer versions of Verilator, functions with delays are not legal, which causes a compile error:

%Error: /path-to-difftest/src/test/vsrc/common/SimJTAG.v:52:17: Delays are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4)
                                                                                           : ... note: In instance 'SimTop'
   52 |    wire         #0.1 __jtag_TDO = jtag_TDO_driven ?
      |                 ^
        ... See the manual at https://verilator.org/verilator_doc.html?v=5.041 for more assistance.
%Error: Exiting due to 1 error(s)

As the delay not be useful in verilator, thus remove it.

[klin02]

I am not sure why we add wire delay for SimJTAG, maybe @poemonsense know about it?

[cyyself]

I am not sure why we add wire delay for SimJTAG, maybe @poemonsense know about it?

Maybe just copied from rocket-chip: https://github.com/chipsalliance/rocket-chip/blob/master/src/main/resources/vsrc/SimJTAG.v

[poemonsense]

The file was brought from https://github.com/chipsalliance/rocket-chip/blob/master/src/main/resources/vsrc/SimJTAG.v.

Which verilator version are you using? I'm using v5.042 and it works.

If this is a serious issue, we may need to fix in the upstream first to ensure its correctness, given that we don't know why

[cyyself]

The file was brought from https://github.com/chipsalliance/rocket-chip/blob/master/src/main/resources/vsrc/SimJTAG.v.

Which verilator version are you using? I'm using v5.042 and it works.

If this is a serious issue, we may need to fix in the upstream first to ensure its correctness, given that we don't know why

I'm also using v5.042.

[poemonsense]

Are you using the build scripts in difftest? Would you mind try https://github.com/OpenXiangShan/rocket-chip/tree/dev-difftest

This is the case we are running in DiffTest CI.

The command was like:

time -avp -o /home/xuyinan/rocket/rocket-chip/build/time.log verilator --exe -O3 --cc --top-module SimTop +define+VERILATOR=1 +define+PRINTF_COND=1 +define+RANDOMIZE_REG_INIT +define
+RANDOMIZE_MEM_INIT +define+RANDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_DELAY=0 -Wno-STMTDLY -Wno-WIDTH --max-num-width 150000 --assert --x-assign unique --output-split 30000 --output
-split-cfuncs 30000 -I/home/xuyinan/rocket/rocket-chip/build/rtl -I/home/xuyinan/rocket/rocket-chip/build/generated-src -CFLAGS "-I/home/xuyinan/rocket/rocket-chip/difftest/src/test/
csrc/common -I/home/xuyinan/rocket/rocket-chip/difftest/config -DNOOP_HOME=\\\"/home/xuyinan/rocket/rocket-chip\\\" -I/home/xuyinan/rocket/rocket-chip/build/generated-src -I/home/xuy
inan/rocket/rocket-chip/difftest/src/test/csrc/plugin/include -I/home/xuyinan/rocket/rocket-chip/difftest/src/test/csrc/difftest -DREF_PROXY=SpikeProxy -DREF_HOME=\\\"/home/xuyinan/r
ocket/riscv-isa-sim\\\" -I/home/xuyinan/rocket/rocket-chip/difftest/src/test/csrc/plugin/spikedasm -I/home/xuyinan/rocket/rocket-chip/difftest/src/test/csrc/emu -DNUM_CORES=1 -I/home
/xuyinan/rocket/rocket-chip/difftest/src/test/csrc/verilator -DVERILATOR --std=c++17 -DVERILATOR_4_210" -LDFLAGS "-lz -lzstd -ldl" -CFLAGS "\$(PGO_CFLAGS)" -LDFLAGS "\$(PGO_LDFLAGS)"
 -o /home/xuyinan/rocket/rocket-chip/build/verilator-compile/emu +define+DIFFTEST --instr-count-dpi 1 --no-timing +define+VERILATOR_5 --quiet-stats --Mdir /home/xuyinan/rocket/rocket
-chip/build/verilator-compile /home/xuyinan/rocket/rocket-chip/build/rtl/SimTop.sv /home/xuyinan/rocket/rocket-chip/difftest/src/test/vsrc/common/SimJTAG.v /home/xuyinan/rocket/rocke
t-chip/difftest/src/test/vsrc/common/ref.v /home/xuyinan/rocket/rocket-chip/difftest/src/test/vsrc/common/assert.v [more cpp files here]