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2 changes: 1 addition & 1 deletion src/cpu/o3/issue_queue.hh
Original file line number Diff line number Diff line change
Expand Up @@ -260,7 +260,7 @@ class Scheduler : public SimObject
CPU* cpu;
MemDepUnit* memDepUnit;
LSQ* lsq;
const int intel_fewops = 4;
const int intel_fewops = 8;

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P1 Badge Keep FEW-op threshold aligned with configured issue width

Raising intel_fewops to a hardcoded 8 makes exec_stall_cycle count cycles as “few uops” even when narrower cores are fully utilized, which skews the Topdown breakdown (coreBound/memoryBound) that is derived from these counters in src/cpu/o3/cpu.cc (lines 503-521) and normalized by cpu->issueWidth (lines 479-490). This is a regression for any config with issue width below 8 (for example, the decodeWidth = 4 Xiangshan ECore configs), where full-issue cycles will now be misclassified as stalls.

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bool old_disp = false;
const int intRegfileBanks;

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