DDR 8 channel 100delay

[edwu186]

Summary by CodeRabbit

• Configuration Updates

  • Default DRAM configuration across simulation workflows and scripts switched to an 8-channel DDR4-3200 profile.
  • A new 8-channel DDR4-3200 DRAM configuration profile was added.

• Performance

  • Increased memory bus response latency parameter, affecting memory access timing and bandwidth characteristics.

_{✏️ Tip: You can customize this high-level summary in your review settings.}

[coderabbitai]

📝 Walkthrough

Walkthrough

Updated the DRAM simulation from a 2-channel to an 8-channel DDR4-3200 configuration across scripts; added a new DRAMsim3 ini file for the 8-channel board; and increased the L3-to-memory bus response_latency from 78 to 224.

Changes

Cohort / File(s)	Summary
DRAM configuration path updates \.github/workflows/autotest/gem5-vec.cfg, \.github/workflows/autotest/gem5.cfg, configs/common/xiangshan.py, configs/example/se.py, util/memory_check/run-xs-with-valgrind.sh, util/pgo/basic_pgo.sh, util/runse.sh	Replaced references to xiangshan_DDR4_8Gb_x8_3200_2ch.ini with xiangshan_DDR4_8Gb_x8_3200_8ch.ini so DRAMsim3 uses the 8‑channel ini across workflows and scripts.
New DRAMsim3 ini file ext/dramsim3/xiangshan_configs/xiangshan_DDR4_8Gb_x8_3200_8ch.ini	Added new DDR4 8Gb x8, 3200 MT/s configuration specifying dram_structure, timing, power, system (channels=8, channel_size, bus_width, queue/refresh/row buffer policies), and other simulator parameters.
Cache/memory bus timing configs/common/Caches.py	Updated L3ToMemBus(CoherentXBar) class attribute response_latency from 78 to 224.

Sequence Diagram(s)

(omitted)

Estimated code review effort

🎯 3 (Moderate) | ⏱️ ~20 minutes

Possibly related PRs

• mem: Add 8 channel ddr profiling #703: Appears to perform the same changeset switching DRAMsim3 from the 2‑channel ini to the new 8‑channel xiangshan_DDR4_8Gb_x8_3200_8ch.ini and updating callers/defaults.

Suggested reviewers

• jensen-yan
• tastynoob

Poem

🐰 Eight lanes hum, the memory wakes,
From two to eight the pathway takes.
New ini sown in configs' bed,
Latency stretched, the bytes now spread.
A hopping rabbit cheers the cores—hip‑hop hooray!

🚥 Pre-merge checks | ✅ 2 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 50.00% which is insufficient. The required threshold is 80.00%.	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (2 passed)

Check name	Status	Explanation
Description Check	✅ Passed	Check skipped - CodeRabbit’s high-level summary is enabled.
Title check	✅ Passed	The title 'DDR 8 channel 100delay' accurately reflects the primary change: updating DRAM configuration from 2-channel to 8-channel mode with modified latency (response_latency from 78 to 224).

_{✏️ Tip: You can configure your own custom pre-merge checks in the settings.}

✨ Finishing touches

• 📝 Generate docstrings

---

---

📜 Recent review details

Configuration used: defaults

Review profile: CHILL

Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between 7db0e69 and 5ba1af3.

📒 Files selected for processing (1)

• configs/common/Caches.py

🚧 Files skipped from review as they are similar to previous changes (1)

• configs/common/Caches.py

⏰ Context from checks skipped due to timeout of 90000ms. You can increase the timeout in your CodeRabbit configuration to a maximum of 15 minutes (900000ms). (1)

• GitHub Check: Quick Build, Unit Tests & Smoke Test

_{✏️ Tip: You can disable this entire section by setting review_details to false in your review settings.}

---

Thanks for using CodeRabbit! It's free for OSS, and your support helps us grow. If you like it, consider giving us a shout-out.

❤️ Share

• X
• Mastodon
• Reddit
• LinkedIn

_{Comment @coderabbitai help to get the list of available commands and usage tips.}

[github-actions]

🚀 Coremark Smoke Test Results

Branch	IPC	Change
Base (xs-dev)	2.1691	-
This PR	2.1360	📉 -0.0331 (-1.53%)

✅ Difftest smoke test passed!

[github-actions]

🚀 Coremark Smoke Test Results

Branch	IPC	Change
Base (xs-dev)	2.1664	-
This PR	2.1364	📉 -0.0300 (-1.39%)

✅ Difftest smoke test passed!