Fix SPI1 dts configuration to resolve TFT MISO read and touch issues on V2 board

[vmanchala-dev]

Description

Fixed SPI1 communication issues on the V2 board for LCD display Id read and touch issue, now ILI9488 display register reads
ILI9488 display register reads
Added below changes

0x190 0x2B   /* spi1_sclk  - RXACTIVE=1, pull disabled | MODE3 */
0x194 0x2B   /* spi1_d0    - RXACTIVE=1, pull disabled | MODE3 */
0x198 0x13   /* spi1_d1    - output, MODE3 */

Disabled internal pull resistors on SCLK and MISO
Enabled RXACTIVE on input signals

Verification

• Display ID read correctly: 0x4033
• SPI register reads stable
• Touch controller issue fixed
• Verified using Saleae logic analyzer

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Note

Low Risk
Small device-tree pinmux tweak limited to SPI1 signal electrical configuration; main risk is unintended SPI timing/electrical side effects on boards relying on the previous pull-up settings.

Overview
Updates the BB-SPIDEV1-00A0_zola.dts SPI1 pinmux to enable RXACTIVE and disable internal pulls on spi1_sclk and spi1_d0 (MISO), replacing the prior pull-up configurations.

This is intended to stabilize SPI read behavior (e.g., TFT register reads / touch controller reads) by changing the electrical characteristics of the clock and input data lines while leaving the rest of the SPI1 overlay unchanged.

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