dts: arm: nuvoton: npcm: fix PWM clock control register mappings #205
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
The PWM clock configurations in npcm.dtsi were incorrectly mapped to PWDWN_CTL registers. According to the NPCM400 hardware specification, the PWM modules use the following power-down control mappings: ``` Hardware Name Software PWM PWDWN_CTL Register ------------- ------------ ------------------ PWM_A (bit 0) pwm0 PWDWN_CTL2[0] PWM_B (bit 1) pwm1 PWDWN_CTL2[1] PWM_C (bit 2) pwm2 PWDWN_CTL2[2] PWM_D (bit 3) pwm3 PWDWN_CTL2[3] PWM_E (bit 4) pwm4 PWDWN_CTL2[4] PWM_F (bit 5) pwm5 PWDWN_CTL2[5] PWM_G (bit 6) pwm6 PWDWN_CTL2[6] PWM_H (bit 7) pwm7 PWDWN_CTL2[7] PWM_I (bit 0) pwm8 PWDWN_CTL0[0] PWM_J (bit 1) pwm9 PWDWN_CTL0[1] ``` This fix ensures PWM modules are correctly powered on/off through their designated power-down control register bits. Signed-off-by: Tim Lee <CHLi30@nuvoton.com>
maxdog988
merged commit 5c37aa6
into
Nuvoton-Israel:joseph/npcm4_to_npcmx
1 check passed
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
The PWM clock configurations in npcm.dtsi were incorrectly mapped to PWDWN_CTL registers. According to the NPCM400 hardware specification, the PWM modules use the following power-down control mappings:
Hardware Name Software PWM PWDWN_CTL Register
PWM_A (bit 0) pwm0 PWDWN_CTL2[0]
PWM_B (bit 1) pwm1 PWDWN_CTL2[1]
PWM_C (bit 2) pwm2 PWDWN_CTL2[2]
PWM_D (bit 3) pwm3 PWDWN_CTL2[3]
PWM_E (bit 4) pwm4 PWDWN_CTL2[4]
PWM_F (bit 5) pwm5 PWDWN_CTL2[5]
PWM_G (bit 6) pwm6 PWDWN_CTL2[6]
PWM_H (bit 7) pwm7 PWDWN_CTL2[7]
PWM_I (bit 0) pwm8 PWDWN_CTL0[0]
PWM_J (bit 1) pwm9 PWDWN_CTL0[1]
This fix ensures PWM modules are correctly powered on/off through their designated power-down control register bits.