Skip to content
View NoahH190's full-sized avatar

Block or report NoahH190

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. onboarding-start-new onboarding-start-new Public

    Forked from UW-ASIC/onboarding-start

    Welcome to UWASIC! Start here.

    Python

  2. Verilog-Design-Examples Verilog-Design-Examples Public

    Forked from snbk001/Verilog-Design-Examples

    Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversi…

    Verilog

  3. Memory_Game Memory_Game Public

    Verilog

  4. noah-website noah-website Public

    Forked from alishaarora56/alisha-website

    Noah's Personal Website

    HTML