Verilog-basic-programmes

This repository contains basic programs of Verilog HDL like adder,multiplexer etc...

In the description link is given where you can simulate the code and verify the results.

Name		Name	Last commit message	Last commit date
Latest commit History 37 Commits
Arbitary_seq_counter.v		Arbitary_seq_counter.v
D_Flipflop.v		D_Flipflop.v
Demux_dataflow.v		Demux_dataflow.v
Encoder.v		Encoder.v
Full_adder.v		Full_adder.v
Full_adder_struct.v		Full_adder_struct.v
Full_subtractor.v		Full_subtractor.v
Generate_case.		Generate_case.
Generate_if_mux.v		Generate_if_mux.v
Half_adder.v		Half_adder.v
Half_subtractor.v		Half_subtractor.v
JK_Flipflop.v		JK_Flipflop.v
Multiplexer_8:1.v		Multiplexer_8:1.v
PIPO_shift_register.v		PIPO_shift_register.v
PISO_Shift_register.v		PISO_Shift_register.v
README.md		README.md
Ring_counter.v		Ring_counter.v
SIPO_Shift_register.v		SIPO_Shift_register.v
SR_Flip_flop.v		SR_Flip_flop.v
Sequence_detector.v		Sequence_detector.v
T_Flipflop.v		T_Flipflop.v
Universal_logical_Shift_register.v		Universal_logical_Shift_register.v
Universal_updown_counter.v		Universal_updown_counter.v
binar_counter_4bit.v		binar_counter_4bit.v
decade_counter.v		decade_counter.v
decoder.v		decoder.v
demux_dataflow.v		demux_dataflow.v
half_adder_generate _for.v		half_adder_generate _for.v
priority_encoder.v		priority_encoder.v

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