Come with me on an adventure discovering how the logic of the Zilog Z80 computer processing unit works. I'll be diving deep into the following
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Registers - Where all values are stored
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ALU - The arithmetic logic unit. Where all the logic is handled.
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PLA - The programmable logic array. The decoder that reads the operation codes and directs them to the correct logic function
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Timing - the timing of the read, write and other cycles
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Control - The traffic cop directing the bus and control lines
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Putting it all together - Making a Z80 simulated system using VGA, 7 segment displays, 4x4 keypad and serial io using Digital logic simulator.
- Register section completed
- ALU section in progress
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Visual6502 High resolution die shots of the Z80.
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Ken Shirrif's Blog His site reverse engineered the Z80 die.
- Z80 notes Gitub site of his notes on the layout of the Z80 die
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Baltazar Studios Goran Devic's site where he reversed the Z80 die to make a netlist Z80 simulator and a FPGA Z80 soft core. The logic diagrams I use come from this site.
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Z80Explorer Github site of the netlist Z80 simulator where you can see the processing on the Z80 die visually.
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A-Z80 Github site with bdf files for Intel's FPGA to make a Z80 soft core. He includes an example of a working ZX Spectrum.
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Digital The logic simulator used to describe, test and simulate the Z80.