GitHub - MajeedAskari/Pipeline-CPU: 5 Staged Mips pipelined cpu

Name		Name	Last commit message	Last commit date
Latest commit History 26 Commits
MEMControl.v		MEMControl.v
Stall Contol.v		Stall Contol.v
WBControl.v		WBControl.v
adder.v		adder.v
alu-control.v		alu-control.v
alu.v		alu.v
branchunit.v		branchunit.v
codes.txt		codes.txt
control-unit.v		control-unit.v
cpu.v		cpu.v
data-memory.v		data-memory.v
inst-memory.v		inst-memory.v
midregister.v		midregister.v
mux2to1.v		mux2to1.v
pc.v		pc.v
regfile.v		regfile.v
shift-left2.v		shift-left2.v
sign-extend.v		sign-extend.v

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